! Energy Optimization/Design Tradeoffs. ! Design Space Exploration. " Example. ! Sequential MOS Logic. ! Every time output switches 0#1 pay:

(1)

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Lec 17: March 26, 2020 Design Space Exploration, Sequential MOS

Logic

Penn ESE 570 Spring 2020 – Khanna

Lecture Outline

! 

Energy Optimization/Design Tradeoffs

! 

Design Space Exploration

" 

Example

! 

Sequential MOS Logic

2 Penn ESE 570 Spring 2020 – Khanna

Total Power

! 

P

_tot

≈ P

_static

+ P

_dyn

+ P

_sc

Dynamic Power

! 

Every time output switches 0#1 pay:

" 

E = CV

²

! 

P

_dyn

= (# 0#1 trans) × CV

²

/ time

! 

# 0#1 trans = ½ # of transitions

! 

P

_dyn

= (# trans) × ½CV

²

/ time

Charging Power

! 

P

_dyn

= (# 0#1 trans) × CV

²

/ time

! 

Often like to think about switching frequency

! 

Useful to consider per clock cycle

" 

Frequency f = 1/clock-period

! 

P

_dyn

= (# 0#1 trans/clock) CV

²

f

" 

f # units of clock/time

Switching Power

! 

P

_dyn

= (#0#1 trans/clock) CV

²

f

! 

Let a = activity factor a = average #tran

_0#1

/clock

! 

P

_dyn

= aCV

²

f

6 Penn ESE 570 Spring 2020 - Khanna

(2)

Activity Factor

! 

Let a = activity factor

" 

a = average #tran

_0#1

/clock

Penn ESE 570 Spring 2020 - Khanna 7

a = p(out

_i

= 0) p(out

_i+1

= 1) a = N

₀

2

^N

N

₁

2

^N

= N

₀

(2

^N

− N

₀

) 2

^{2 N}

Activity Factor

! 

Let a = activity factor

" 

a = average #tran

_0#1

/clock

a = p(out

_i

= 0)p(out

i+1

= 1) a = N

₀

2

^N

N

₁

2

^N

= N

₀

(2

^N

− N

0

) 2

^{2 N}

Activity Factor

! 

Let a = activity factor

" 

a = average #tran

_0#1

/clock

a = p(out

_i

= 0)p(out

i+1

= 1) a = N

₀

2

^N

N

₁

2

^N

= N

₀

(2

^N

− N

0

) 2

^{2 N}

N=2 N=4

A B AND

0 0 0

0 1 0

1 0 0

1 1 1

Activity Factor

! 

Let a = activity factor

" 

a = average #tran

_0#1

/clock

a = p(out

_i

= 0)p(out

i+1

= 1) a = N

₀

2

^N

N

₁

2

^N

= N

₀

(2

^N

− N

0

) 2

^{2 N}

N=2 N=4

A B AND

0 0 0

0 1 0

1 0 0

1 1 1

a =

3 4 ⋅ 1

4 = 3

16 a=?

Reduce Dynamic Power?

! 

P

_dyn

= aCV

²

f

! 

Which has less dynamic power?

" 

Assume all AND gates min size

A B

C D

O₁

O₂ F

A B

C D O1

O₂ F

Reduce Activity Factor

A B

D C

O1

O₂ F

A B

C D O₁

O₂ F

Tree Chain

a = p(out

_i

= 0)p(out

i+1

= 1) a = N

0

2

^N

N

1

2

^N

= N

0

(2

^N

− N

0

) 2

^{2 N}

all switch 0#1

(3)

Reduce Activity Factor

A B

C D

O1

O₂ F

A B

C D O₁

O₂ F

Tree Chain

a = p(out

_i

= 0)p(out

i+1

= 1) a = N

0

2

^N

N

1

2

^N

= N

0

(2

^N

− N

0

) 2

^{2 N}

3/16

3/16 all switch

0#1

Reduce Activity Factor

A B

D C

O1

O₂ F

A B

C D O₁

O₂ F

Tree Chain

a = p(out

_i

= 0)p(out

i+1

= 1) a = N

0

2

^N

N

1

2

^N

= N

0

(2

^N

− N

0

) 2

^{2 N}

3/16

3/16 15/256 all switch

0#1

Reduce Activity Factor

A B

C D

O₁

O2

F A B

C D O₁

O₂ F

Tree Chain

3/16 7/64

15/256

a = p(out

i

= 0)p(out

i+1

= 1) a = N

₀

2

^N

N

₁

2

^N

= N

₀

(2

^N

− N

0

) 2

^{2 N}

all switch 0#1

Reduce Activity Factor

A B

D C

O₁

O2

F A B

C D O₁

O₂ F

Tree Chain

3/16 7/64

15/256

a = p(out

i

= 0)p(out

i+1

= 1) a = N

₀

2

^N

N

₁

2

^N

= N

₀

(2

^N

− N

0

) 2

^{2 N}

3/16

3/16 15/256 all switch

0#1

Total Power Summary

! 

P

_tot

= P

_static

+ P

_sc

+ P

_dyn

! 

P

_sw

= P

_dyn

+ P

_sc

≈ a(C

_load

V

²

f)

! 

P

_tot

≈ a(C

_load

V

²

f) + VI

^’_s

(W/L)e

-Vt/(nkT/q)

! 

Let a = activity factor a = average #tran

_0#1

/clock

Design Tradeoffs

Power vs Speed (Energy vs Delay)

(4)

Reduce V _dd

! 

What happens as reduce V?

" 

Energy?

" Static

" Dynamic

" 

Delay?

Reduce V _dd

20

! 

τ

gd

impact?

τ

_gd

= CV

_dd

I

_d

Reduce V _dd

21

! 

τ

_gd

impact?

τ

_gd

= CV

_dd

I

_d

I

_d

= 1 2 ( ) ^µC

^ox

( ^{W L} ) ( ^V

^gs

^−V

^th

)

²

Reduce V _dd

22

! 

τ

_gd

impact?

τ

_gd

= CV

_dd

I

_d

I

_d

= 1 2 ( ) ^µC

^ox

( ^{W L} ) ( ^V

^gs

^−V

^th

)

²

τ

_gd

= CV

_dd

I

_d

= CV

_dd

( ) 1 2 ^µC

^ox

( ^{W L} ) ( ^V

^gs

^−V

^th

)

²

Reduce V _dd

23

! 

τ

gd

impact?

τ

_gd

= CV

_dd

I

_d

I

_d

= 1 2 ( ) ^µC

^ox

( ^{W L} ) ( ^V

^gs

^−V

^th

)

²

τ

gd

= CV

_dd

I

_d

= CV

_dd

( ) 1 2 ^µC

^ox

( ^{W L} ) ( ^V

^gs

^−V

^th

)

²

τ

gd

∝ 1 V

_dd

Reduce V _dd

24

! 

τ

gd

impact?

τ

_gd

= CV

_dd

I

_d

I

_d

= 1 2 ( ) ^µC

^ox

( ^{W L} ) ( ^V

^gs

^−V

^th

)

²

τ

gd

= CV

_dd

I

_d

= CV

_dd

( ) 1 2 ^µC

^ox

( ^{W L} ) ( ^V

^gs

^−V

^th

)

²

τ

gd

∝ 1

V

_dd

E

_dyn

= CV

_dd²

(5)

Reduce V _dd

25

! 

τ

gd

impact?

τ

_gd

= CV

_dd

I

_d

I

_d

= 1 2 ( ) ^µC

^ox

( ^{W L} ) ( ^V

^gs

^−V

^th

)

²

τ

gd

= CV

_dd

I

_d

= CV

_dd

( ) 1 2 ^µC

^ox

( ^{W L} ) ( ^V

^gs

^−V

^th

)

²

τ

gd

∝ 1

V

_dd

× E

_dyn

= CV

_dd²

#

€

Eτ

²

≈ Const 2

Reduce V _dd

26

! 

τ

gd

impact?

τ

_gd

= CV

_dd

I

_d

I

_d

= v

_sat

C

_ox

W V (

_gs

−V

_th

−V

_DSAT

2 )

Eτ ≈ Const

Slow Down

! 

P

_dyn

= aCV

²

f

! 

P

_stat

= IV

! 

What happens to energy as we reduce clock frequency by half?

" 

Example: CMOS circuit consumes equal dynamic and

leakage power, X. No short circuit power. The energy consumed in T seconds is 2XT.

Slow Down

! 

P

_dyn

= aCV

²

f

! 

P

_stat

= IV

! 

What happens to energy as we reduce clock frequency by half?

" 

Example: CMOS circuit consumes equal dynamic and

leakage power, X. No short circuit power. The energy consumed in T seconds is 2XT.

" E = PT = (X+X)T = 2XT

Slow Down

! 

P

_dyn

= aCV

²

f

! 

P

_stat

= IV

! 

What happens to energy as we reduce clock frequency by half?

" 

Example: CMOS circuit consumes equal dynamic and

leakage power, X. No short circuit power. The energy consumed in T seconds is 2XT.

" 

New energy: (X/2 + X)2T = 3XT

" 

Increased energy!

Slow Down

! 

P

_dyn

= aCV

²

f

! 

P

_stat

= IV

! 

What happens to energy as we reduce V

_dd

by half?

" 

Reducing V

_dd

slows our gates down, so assume the clock

frequency reduces by half.

" 

Assume leakage current stays the same.

" 

Example: CMOS circuit consumes equal dynamic and

leakage power, X. No short circuit power. The energy consumed in T seconds is 2XT.

(6)

Slow Down

! 

P

_dyn

= aCV

²

f

! 

P

_stat

= IV

! 

What happens to power contributions as we reduce V

_dd

by half?

" 

Reducing V

_dd

slows our gates down, so assume the clock

frequency reduces by half.

" 

Assume leakage current stays the same.

" 

Example: CMOS circuit consumes equal dynamic and

leakage power, X. No short circuit power. The energy consumed in T seconds is 2XT.

! 

New power: (X/8 + X/2)2T = 5XT/4 = 1.25XT

Idea

! 

Tradeoff

" 

Speed

" 

Switching energy

" 

Leakage energy

! 

Energy-Delay tradeoff: Eτ

²

Design Space Exploration

Design Problem

! 

Function: Identify equivalence of two 32bit inputs

! 

Optimize: Minimize total energy

! 

Assumptions: Match case uncommon

" 

Ie. Most of the time, the inputs won’t be matched

! 

Deliberately focus on Energy to complement HW 7 where you are minimizing delay

" 

…but will still talk about delay

Idea: Design Space Explore

! 

Identify options

" 

All the knobs you can turn

! 

Explore space systematically

! 

Formulate continuum where possible

" 

i.e. formulate trends and tradeoffs quantitatively

Problem Solvable

! 

Is it feasible?

" 

First, make sure we have a solution so we know our main

goal is optimization

! 

How do we decompose the problem?

(7)

Problem Solvable

! 

Is it feasible?

" 

First, make sure we have a solution so we know our main

goal is optimization

! 

How do we decompose the problem?

" 

Bit-by-bit comparison

! 

What does this look like built out of nand2 gates and inverters?

Bit-by-bit Comparison with NAND2

A

B O

Combine Bit Comparison Outputs

Single Gate Match Condition

! 

Design a single gate for match comparison

Single Gate Match Condition

! 

Design a single gate for match comparison

Out = A⋅ B + A⋅ B

Comparison

-Assume inputs driven with min size inverters -C

_d

=0

-R

_un

=R, C

_g

=C

(8)

Combine Bit Comparison Outputs

Total Power

! 

Static CMOS:

" 

P

_tot

≈ a(C

_load

+2C

_sc

)V

²

f+VI

^’_s

(W/L)e

-Vt/(nkT/q)

! 

Ratioed Logic:

" 

P

_tot

≈ a(C

_load

+2C

_sc

)V

²

f

+p(V

_out

=low)V

²

/R

_pon

+(1-p(V

_out

=low))VI

^’_s

(W/L)e

-Vt/(nkT/q)

! 

What can we do to reduce power?

Knobs

! 

What are the options and knobs we can turn?

Design Space Dimensions

! 

Topology

" 

(A) Gate choice, logical optimization

" 

(B) Fanin, fanout, (C) Serial vs. parallel

! 

Gate style / logic family

" 

(D) CMOS, Ratioed (N load, P load), Pass Logic

! 

(E) Transistor Sizing

! 

(F) Vdd

! 

(G) Vth

Topology

! 

(A) Gate choice. What gates might we build?

Topology

! 

(A) Gate choice. What gates might we build?

(9)

Topology

! 

(B) Higher fanin?

-Reduced switching because we know inputs don’t match often # small a -Increased C_load on gates # P_dyn goes up

Topology

! 

(C) Serial-Parallel?

-As soon as mismatch is found all switching stops # small a

-Increased delay, but our goal here is to minimize power

(D) Logic Family

! 

Considerations for each logic family?

(D) Logic Family

! 

Considerations for each logic family?

" 

CMOS

" 

Ratioed with PMOS load

" 

Ratioed with NMOS load

! 

Ratioed Logic

" 

Reduced C

_loads

result in lower switching power (P

_dyn

$)

" 

Increased steady-state power

(E) Sizing

! 

How do we want to size gates?

(E) Sizing

! 

How do we want to size gates?

" 

Sizing transistors up will reduce delay #

" 

Reduces short circuit power

" 

Increases dynamic power

€

E = V

dd

× I

peak

× t

sc

× 1 2

#

$ % &

' (

#

$ % &

' (

(10)

(F) Reduce Vdd

! 

What happens as reduce V?

" 

Energy?

" Dynamic $

" Static $

" 

Switching Delay? %

& 

τ

gd

=Q/I=(CV)/I

& 

I

_d

=(µC

OX

/2)(W/L)(V

_gs

-V

_TH

)

²

& 

τ

gd

impact?

& 

τ

gd

α 1/V

& 

Limit on V

_dd

?

(G) Increase V _th ?

! 

What is impact of increasing threshold on

" 

Dynamic Energy? $

" 

Leakage Energy? $

" 

Delay? %

V

_gs

I

d

V

_t

V

t

V

dd

Ideas

! 

Three components of power

" 

P

_tot

= P

_static

+ P

_dyn

+ P

_sc

! 

We know many things we can do to our circuits

! 

Design space is large

! 

Systematically identify dimensions

! 

Identify continuum (trends) tuning when possible

! 

Watch tradeoffs

" 

…don’t over-tune

Sequential MOS Logic

Classes of Logic Circuits

59 Combinational Circuits:

a. Current Output(s) depend ONLY on Current Inputs.

b. Suited to problems that can be solved using truth tables.

Sequential Circuits or State Machines:

a. Current Output(s) depend on Current Inputs and Past Inputs via State(s).

b. Suited to problems that are solved by completing several steps using current inputs and past outputs in a specific order or a sequential manner.

Sequential Circuit (or State Machine) Construct

60

-> Register is used to Store Past Values of State(s) and Output(s)

-> Synchronous Sequential Circuit – clock, outputs change with clock event

-> Asynchronous Sequential Circuit – no clock, outputs change after inputs change

V

_o1

V

_o2

. . . .

V

_o3

Present State

Next State

Inputs Outputs

Clock

REGISTER

(11)

Synchronous Discipline

! 

Add state elements (registers, latches)

! 

Compute

" 

From state elements

" 

Through combinational logic

" 

To new values for state elements

Static Bistable Sequential Circuits

62 Basic Cross-

coupled Inverter pair

Q Q

63 Basic Bistable Cross-coupled Inverter Pair has no means to apply input(s)

to change the circuit's State.

Basic Cross- coupled Inverter

pair Q

Q

V

_OH

= V

_DD

V

_OL

= 0 maintain stable state.

STATIC: V

_DD

and GND are required to maintain a stable state.

Static Bistable Sequential Circuits

Basic Sequential Circuits (Cells)

! 

Latches

! 

Registers

Latch

65

Q = CLK ⋅Q + CLK ⋅ In

! 

Level-sensitive device

! 

Positive Latch

" 

Output follows input if

CLK high

! 

Negative Latch

" 

Output follows input if

CLK low

Register

66

! 

Edge-triggered storage element

! 

Positive edge-triggered

" 

Input sampled on

rising CLK edge

! 

Negative edge- triggered

" 

Input sampled on

falling CLK edge

(12)

Shift Register

! 

How do you make a shift register out of latches?

Positive-Edge Triggered Register

! 

Build register from pair of positive latches

! 

What happens when φ

₀

is high?

! 

What happens when φ

₁

is high?

Q_M

Positive-Edge Triggered Register

! 

Build register from pair of positive latches

QM

Positive-Edge Triggered Register

! 

Build register from pair of positive latches

! 

What could go wrong if clocks overlap?

QM

Positive-Edge Triggered Register

! 

Build register from pair of positive latches

! 

Control with non-overlapping clocks

Timing Hazards

(13)

Clocking Discipline

! 

Follow discipline of combinational logic broken by registers

! 

Compute

" 

From state elements

" 

Through combinational logic

" 

To new values for state elements

! 

As long as clock cycle long enough,

" 

Will get correct behavior

Latch Timing Issues

! 

t

_su

=time data (D) must be valid before CLK edge

! 

t

_plogic

=worst case propagation delay of logic

! 

t

_c-p

=worst case propagation delay of latch

Latch Timing Issues

! 

t

_cdregister

=minimum propagation delay of latch

! 

t

_cdlogic

=minimum propagation delay of logic

! 

t

_hold

=time data (D) must stay valid after CLK edge

Timing Example

(14)

Timing Example

Clocking Highlights

! 

Clock discipline simplifies logic composition

" 

Abstracts many internal timing details

" 

Just concerned with making clock period long enough

! 

Breaking logic up with registers allows circuit to run at high frequency

" 

Inputs decoupled from outputs

! 

Design Discipline – keeping data stable around clock edge

" 

Setup, hold time – determined by latch circuit

" 

Worst case and minimum Clk#Q delay for latch

Ideas

! 

Synchronize circuits

" 

to external events (eg. Clk)

" 

disciplined reuse of circuitry

! 

Leads to clocked circuit discipline

" 

Uses state holding element (eg. Latches and registers)

" 

Prevents

" Timing assumptions

" (More) complex reasoning about all possible timings

Admin

! 

HW 7 due 4/3

" 

Only choose the multiplier if you have designed an adder

before…

" 

…but you don’t have to

" 

Start yesterday!

" 

Will take time and organization

" 

Remember to test each gate/block for functionality before

connecting them together

" 

See references in Canvas Files

" 

Midterm on Monday

" 