Self-Checking Combinational Circuits with Unidirectionally Independent Outputs

(1)

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Self-Checking

Combinational Circuits with

Unidirectionally

Independent

Outputs

A. MOROSOW a’*, V. V. SAPOSHNIKOV

b,

VL. V.SAPOSHNIKOVb_and_M._GOESSELa

DepartmentofComputerScience,Fault-TolerantGroupattheUniversityPotsdam,P.O. Box601553, Potsdam 14415,Germany;

Railway-TransportationUniversityofSt. Petersburg,

_fir.

Moskovskij9,Sankt-Petersburg,Russia

Inthispaperweproposeastructure dependentmethodfor the systematic design ofa self-checkingcircuit which iswelladaptedtothefault model of single gate faults andwhich

canbeused in testmode.

According to the fault model considered, maximal groups of independent and unidirectionally independent outputs ofanarbitrarily given combinational circuit are

determined. A parity bit is added to every group of independent outputs. A few

additionaloutputsareaddedtoevery group of unidirectionally independent outputs.In

theerrorfree case, these groupsof unidirectionalindependent outputs togetherwiththeir

correspondingadditionaloutputsareelements ofaunidirectional errordetecting code; forexample,aBergercodeor anr-out-of-s code.

Itisdemonstratedhowthepairsof (unidirectionally) independent outputs ofagiven

circuit can be determined. A simple heuristic solution for this problem based on a

modified circuitgraphisalso given.

The maximal classes of(unidirectionally) independent outputscan becomputed as

cliques ofadependencygraph where the nodes of the grapharetheoutputsofthecircuit.

The applicability of the proposed methodisdemonstrated for theMCNCbenchmarks

circuits.

Keywords." Self-Checkingcircuits,Independent and unidirectionally independent outputs,

Parity-code,Berger-code

1.

INTRODUCTION

The design of self-checking circuits[1-3] and

the combination of methods for on-line error

detection orconcurrentchecking and testing is of great interest now

(s.e.g.[4]).

It was first proposed

in[5]that on-lineerrordetection byduplication and comparison be combined with testing to use the same hardware in different operational modes. These ideas were further developed in[6’7] for an

*Corresponding author.

333

arbitrary predictionfunction and for independent

outputsin

[8].

Parity predictionformutuallydisjoint

groups of outputs of combinational circuits is a

special case ofthis approach

[9’1].

These methods,

however, are generally not well-adapted to the

specific structure of the monitored circuit and the

technical faultmodel.

A

method for thedesign of

self-checking and self-testing circuits which is to

some extent adapted to the fault model of single gatefaults,isgivenin

[8].

In

thatpaper,independent

(2)

outputs ofthemonitored combinationalcircuitare the groups of outputs for which the parity is

computed, duplicated, inverted, and compared

with the parities ofthe originalcircuit.

In

normal operation mode,every single gate fault forcing an

output to be erroneous for the first time will be detected.

As

well, every single gate fault will be detected intestmode.

In

reality, however,there are

only very few cases where all the outputs of a

circuitcanbe combinedintogroups ofindependent outputs ofareasonablesizewhich are implemented

by completelydifferent gates.

In

[11],

weakly independent outputs are used

instead of independent outputs for the design of

self-testing circuits.

Low

cost implementations of

self-testing circuits are very often possible,

but

in

on-line mode faults may only be detected with

somedegree of latency andthe circuits arenot

self-checking.

As

a generalization of

[8],

we

propose

in this

paper a structure dependent method for the

systematic design of self-checking combinational circuits which iswell-adaptedtothe faultmodelof single gate faults and the structure of the

con-sidered circuit.

Groups

ofindependent outputsas

well as groups of unidirectionally independent

outputs are determined.

Two

outputs are unidi-rectionally independent with respect to a given fault if, in the presence of this fault either both

outputs arecorrect, onlyone outputis erroneous,

orboththe outputsareunidirectionally erroneous.

In

normaloperationmode,theproposedcircuits

are self-checking with respect to all single gate

faults.

In

test mode, these error detection circuits guaranteea 100% faultcoveragefor all nonredun-dantsinglestuck-at-

0/1

faults.

In

this paper, a given combinational circuit is

considered.

In

[12]agiven circuit is modifiedbyuse ofaspecial input(output)encoding. Theproposed

encoding technique guarantees that all internal

single stuck-at faults as well as all single stuck-at

faults of the input lines willresulteither insinglebit

errors or in unidirectional multibit errors of the outputs of the modified circuit. The rest of the paper is organizedasfollows.

In

section2,the basic notions and notations such

as unidirectionally independent outputs, maximal

groupsof tlnidirectionally outputs, and generalized

circuit graph are given. Basic theorems useful for the determination of independent outputs and unidirectionally independent outputs are also pre-sented.

In

section 3, it is shown how independent and unidirectionally independent outputs can be

used to design self-checking circuits.

A

few addi-tional outputs are added to every group of unidirectionally independent outputs.

In

the error

free case, thesegroupsof unidirectionally

indepen-dent outputs are elements of an error detecting

codewhichdetects all unidirectionalerrors.

Every

group of independent outputs is checked by a

parity bit.

In

section4,it is explained how pairs of

(unidirectionally) independentoutputs canactually

be determined. The determination of maximal

groups of (unidirectionally) independent outputs

can be reduced to the standard graph-theoretical

problemofthedeterminationofmaximal cliques of

adependency graph,wherethe nodesofthegraph

are theoutputs of thecircuit considered.

In

section 5 experimentalresultsforbenchmark circuitsare given.

2. BASIC

NOTIONS AND NOTATIONS

In

thispaperweconsideracombinational circuit

fc

with n binary inputsx,...,Xn and m binary

out-pUtsyl

f(xl,..., Xn),...,

Ym

fm(Xl,..., Xn),where

fl,...,fro are n-ary Boolean functions.

Let

x=

(x

l,...,

Xn),

andy (y,...,

Ym).

The setof technical faults consideredisdenoted

by

b=

{b0,

b,...,

bK},

where

_b0

denotes the

ab-senceofafault.

Theoutput_Yiunder input x in the presenceofa

fault

bj

E

_b

is describedby

Yi,j

fi

(bj,

x).

Then,for thecorrectoutput in the absence ofa

fault, wehave

(3)

The notionofunidirectionally independent

out-putsis introduced inthe following definition.

DEFINITION The outputs Yi and Yk are called

unidirectionally independent with respect to the fault

Cj

E andwith respect to a subset

X

c_

X

of the inputset

X

ifwehave, for xE

X,

either

1. fi(x)

fi(j, x)

and

f(x)

f(j, x)

or

2.

_{(fi(x)--fi(bj, x)}

and

fk(X) fk(bj, X))

or (fi(x)-7/=

fi(j, x)

and

fk(X)

fk(j, X))

or

3.

fi(x)#fi(j,x)

and

_fk(x)fk(j,x)

and fi(x)=

fk(X).

According to this definition, two outputs are unidirectionally independent if they are both correct, ifonlyoneof them iserroneous,orifthey

are both unidirectionally erroneous.

In

the last

case,bothoutputsarechanging from0to orfrom

toO.

Independent outputs are a special case of

unidirectionally independent outputs.

Outputs

are

independent if only the conditions and 2 of

Definition are fulfilled. Thus two outputs are

independent ifthey are either both correct or if

onlyoneof them is erroneousat atime.

In

thefollowingwesometimesomitthe subset

X,

especially if this subset is not specified.

Now

we

generalize the definition ofa pair of

unidirection-ally independent outputs with respect to a set of

faults andaset of outputs.

DEFINITION 2 The outputs Yi and Yk are called

unidirectionally independent withrespecttoaset

of faults if these outputs are unidirectionally independent with respecttoeveryfault

Cj

.

DEFINITION 3 The outputs Yi,’’’,Yir form a

group of unidirectionally independent outputs if

every pair of these outputs is unidirectionally

independent.

Similar definitions can be given for independent outputs.Independent outputscanbe determinedby

useof the generalized circuitgraphintroduced in

[9].

In

a similar way, unidirectionally independent outputs can be determined by a modification of

this generalized circuit graph. This will be

explained now.

A

combinational circuit C can be described by

the connections between outputs and inputs of its

logical gates. The gates and the direct outputs of

the circuit are called "elements" of the circuit. These elements can be combined into maximal

classes

_Ci

of elements with one output. The

maximal classes

_Ci

are identified with the nodes

Ni

of the generalized circuitgraph G.

A

node

_N1

of

this graph G is connected with a node

_N2

by an

directededgedirectedfrom

_N1

to

_N2

ifthe output

ofthe class

_C1

isconnectedto one of the inputs of the gates of the class

C2.

The maximal classes of elements with one output corresponding to the nodes of the generalized circuit graph can be determinedasfollows"

1. Create a subset for each non-fanout output of

thecircuit, and markeachelement.

2. If theoutputofan element isconnected onlyto

marked elements of a single, already existing

subset, addtheelementtothe subset andmark

the

element.

3. Ifthe outputofanelementisconnectedonlyto

already marked elements not all belonging to

thesamesubset markthiselement andcreate a

newsubset containingthiselement. The element

isthe outputof thenewlyopenedsubset.

4. Continue until all elements are marked and

belongto asubset.

In

thenextstep thecircuitgraph G

(N, V)

will

be modified into the modified circuit graph

G

=(N’, V’).

In

addition to the nodes N of the

circuit graph

G,

a node nl,...,nm is assigned to

everyoutputYl,...,Ymof the circuit

_ft.

Forthe set

N’

of nodesof

G’,

wehave

N’=

N

tA

{nl,...,

nm}.

In

the modified circuitgraph G

t,

the nodes Ni,

Nk

E

N

areconnected byanon-marked edgeif there isa

pathfrom the output element of the node

Ni

to one

of the inputs of the output element of

Nk

.with

an

even number of inversions. The nodes Ni,

Nk

EN

areconnected by amarked edge ifthereis a path

from theoutputelement ofthe node

_Ni

tooneof the inputs of the output element of

Nk

with an odd

(4)

number of inversions. Inversion of the output of theoutput element of

_Ni

aswellasinversionsatthe input of the output element of

Nk

are taken into account. Inversions at an input of the output element of

_Ni

aswellasinversions of theoutput of

the output element of

_Nk

are not considered for

the marking of the edge from

_Ni

to

_Nk.

Thus,

twonodes of the modifiedgraph

G’

areconnected

by at most two edges, a marked one and an

unmarkedone.

As

an example we consider the combinational

circuit of Fig. 1, which implements the following

Xl X2

fiveBoolean functions:

Yl

("nXl)X2X3(x4)V

(x

V

X2)X3X4

k/

_(X1)

_(-’nX3)X4

Y2

-(Xl

V

x2)

V

XlX3(-’nx4)

k/Xl

(x3)x4

V

_(Xl

V

x2)(-nx3)(-x4)

Y3

(x3

V

x4)((’Xl)(x2)V (Xl)X3(-x4))

Y4

(Xl)(x2) k/Xl(X3)X4

V

XlX3(’-nx4)

Y5

-(x3

V

x4)

V

(-xl)

V

(-x2).

The modifiedgeneralizedcircuitgraphis shown in Fig. 2. AccordingtoFig.2,twoedgesaredrawn

Yl

Y2

Y3

23-)

y5

(5)

N1

N$

nl

N2

N7

N9

n2

N10

n3

N5

_Nil

N6

N12

n5

FIGURE2 Modified generalizedcircuitgraph of the examplecircuitof Fig.1.

fromthenode

_N3

to the node

_N9.

The first edge

corresponds toa pathwith one inversion

(an

odd

number ofinversions)fromelement3toelement 20 viaelement 9. The secondedgeviaelement 11 has

noinversion

(an

evennumberof inverversions).

Similarly, as in

[9],

anode

_Ni

of the modified

gen-eralized circuit graph is called structural essential for the node

_Nk

if thereis atleast onepathfrom

_Ni

to

Nk.

If thereis nopath from

Ni

to

_Nk

the node

_Ni

iscalled structural non-essential for the node

Nk.

The output of the output element ej of the

maximal class

_C

corresponding to the node

_N

willbe denotedbyzj.Theupperindex rof

e

isthe

number of the element in the circuit

_fc

if the elementsofthe circuit are numbered.

We

are mainly interested in outputs which are

(unidirectionally) independent with respect to

functionalfaultsof single gates (single gate

faults).

The maximal classes of elements with one output

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DEFINITION 4 The outputs _Yi and Yk are called

(unidirectionally) independent with respect to the node

Nj

if these outputs are (unidirectionally)

independent with respect to all single gate faults withinthe maximal class

Cj.

PROPOSITION The outputs Yi and Yk are

unidi-rectionally independent withrespecttothe node

_N

of the generalized circuitgraphif andonlyifwehave

dyi dyk

(Yi

Yk)

0.

Fi,k;j

_jj"

dzj

(1)

Therebyzjis theoutputof theoutputelement

e

of

the maximal class

_C

correspondingtothe nodeNj.

Proof

A

faultwithintheclass

Cj

whichforcesan

output_{Yi to}be erroneousforsomex EX necessarily

changesthe output

zj(x)

of

Cj

into

zj(x),

andfor

every input xEX there exists a single gate fault

within

Cj

which forces

zj(x)

to be

-zj(x). (For

z(x)

(0),

astuck-at-0

(1)

fault oftheoutputgate of

_C

results inan outputof 0

(1)).

The inputs of

fc

for which achangeof theoutput

zjof

Cj

resultsinachangeof the outputYs,s i,k,

are determined by

dys/dzj(x)=l.

Thus

dyi/

dzj(x).dyk/dZj(X)=

determines the inputs for

whichachange

ofzj

results inasimultaneouschange

of both the outputs Yi andYk, respectively,yi(x)

yk(X)--- determines the inputs forwhich we have

yi(x)=-yk(x), and

dyi/dzj(x).dyk/dzj(x)(yi(x)

@

yk(x))-

determines the inputs for which a

change of zj simultaneously changes the outputs

yi(x) andyk(x) in different directions. From these equationswe conclude

(1).

For independent

outputs,

wehave thefollowing

proposition.

PROPOSITION The outputs Yi,and Yk are

inde-pendentwithrespecttothe node

Nj

of the

general-izedcircuitgraphif andonlyifwehave

dyi.

dyk

_0.

(1’)

F’

i,k;j

dzj

For

practical applications, the following sufficient conditions for the determination of

(unidi-rectionally)independentoutputs with respect to a

node

_N

of the modified generalized circuit graph

areofinterest.

CONDITION2 The outputs_YiandYkare

unidirec-tionallyindependentwith respecttothe node

Nj

if 1.

_N

isstructural non-essential foratleast oneof

the outputnodesniornk,

or

2. all thepath’sfrom

_Ni

toniand from

N

to ngin

the modifiedgeneralized Graph

G’

containeither

an evennumberof markededgesor anodd number

ofmarkededges.

CONDITION2 The outputsYiand ygare

indepen-dent withrespectto the node

_N

if

Nj

isstructural non-essential foratleastone of theoutputnodesni

and

_n.

Example

By

use of Condition 2, the _{outputs Y}

and

_YE

can be dependentwith respect to thenode

N3, and the outputs y3 and Y5 can be dependent

withrespectto the node

_N4.

To

decide whetheror

not they are unidirectionally independent, we

compute dye dyl x3x4

(-nx1)x

V

(x1)x4

Vx3x4,

dz3

33 dy__3

dy5

(’Xl)(’nX2)

V

(-nXl)X3(-x4),

4

XlX2.

dz4

Nowwecheck condition 1:

dyl

dye2

(Yl

Y2)

x3x4 0

dz3

dY--23" dY---25

_(Y3

@

Ys)

0.

dz4

Thus the outputs ya and _{Y5 are}unidirectionally

independent andthe _{outputs Y} and_{Y2 are} not.

The following theorem is of great practical interest for the determination ofunidirectionally

independent outputs.

PROPOSITION3

Two

outputs _Yi and Yk are

(uni-directionally) independent with respecttothesetof all single gate faults iftheyare(unidirectionally) independent with respect to all nodes Nj of the generalizedcircuit graph.

(7)

3. DESIGN OF SELF-CHECKING

CIRCUITS

WITH

UNIDIRECTIONALLY

INDEPENDENT OUTPUTS

Figure 3 shows the general structure of the

pro-posed self-checkingcircuit.

The outputs Yl,...,’Ym of the circuit

f

are

arranged in h different groups Y1,...,Yh with

Yi

{Yi,..., Yini},

1,...,h, of independent

outputs and unidirectionally independentoutputs.

Every

group

Yi

{Yil,...,

Yini},

i= 1,...,h,willbe

supplemented with some additional outputs

vil,...,vit forming an extended group

Yi

{Yi,-..,

Yini, Vh,...,Vhti

}.

Iftheoutputs ofagroup

Yj

areindependent only

a single parity bit vj is added.

In

Fig. 3

Y

is

assumed to be a group of independent outputs.

Therefore only a single parity bitis addedto this

group.

Iftheoutputs ofagroup

_Yi

are unidirectionally

independent the ti additional outputs are deter-mined in such a way thatthe outputsYi,... ,’Yini,

Vh,...,Vhti areelementsof

an

error detecting code

forall unidirectional errors.

In

Fig. 3 thegroup

_Yh

issupposedtobea group of unidirectionally independent outputs. Thus the outputs Vh,...,_{Vhti are added.}

A

possible error detecting code is a

Berger-code[3] or an s-out-of-r code[141 where s is the

numberof l’s andr isthe number of bits,r ni

+

ti.

To

determinetheelements of ans-out-of-rcode

we.consider all the possible binary ni-tupels of the

(8)

outputsYil,...,Yin of the group

Yi

for xEX.

Let

Mi

(mi)be the maximal

(minimal)

numberof l’s of

thisn-tupels.Then_tiis determinedbyti

Mi

mi.

Itiseasy todetermine the outputs _Vhl _Vhti such

that Yi Yi.i,Vh Vhtiareelementsofan

Mi-out-of-(ni

+

ti) code.

If the number of l’s ofthe considered ni-tuple

Yil,...,Yiniis Ki,mi

_< Ki

_<

Mi, thenexactly

Mi

Ki

additional outputs Vhl,...,Vhti have to be 1. These

_Mi

_Ki

ones canbe arbitrarily distributed

overtheadditional outputsVhl,...,Vhti.

These additional outputs will be jointly

imple-mented by use of an additional combinational circuit

_fca

as shown in Fig. 3.

Every

fault in the

additionalcircuit

_fea

willbe detected.

Every

extended group

Yi

ischecked byuseofa

self-checking code-checker[2’3’15’16] with two

out-puts ui,ui2 with ui =-ui2 in the fault free case. These outputs arecompacted byatwo-rail checker

TRCwith2h inputs and2 outputs

U1

andU2,with

U1

U2

in the fault freecase.

Every

single gate

faultof the circuit

_f

andeveryfault ofthecircuit

_fe

will bedetectedbyanoutput_ui ui2for some ifit

forcesatleast oneof theoutputs of

fc

or

_fa

tobe

erroneousfor the first time. Since_ui _ui: implies

U

_U2

atthe outputofthetwo-railchecker, every

single gate fault of

_f

and

_fca

will be immediately

detected.

In

Fig. 3 the group

_Y

ischeckedbya

self-checkingparity checker

SCP,

and thegroup

Yh

is

checked by a self-checking,code _checker

_SCC

for

the correspondingcode.

4.

DETERMINATION OF INDEPENDENT

AND

UNIDIRECTIONALLY

INDEPENDENT OUTPUTS

If

Ri,

j--

the outputs yi and yj are obviously

independent, if

Ri,j

0

wehavetocompute the expression

Fti,j;k

accordingto

(1’).

Iffor all k with

_Nk

E

Ri,

j,

Ri,

0

we have

Fi,,j;k

0, the

outputsYi andyjare independent.

For

the determination of pairs of

unidirection-ally independent outputs thisprocedurehas tobe

modified.

1’.

To

every node nj, j 1,...,m, we assign two

sets Tj and

Tj

A

node Nk,

Nk

N,

belongs

to

Tj

(T[)

if there exist apath from

_Nk

tonj

with an even

(odd)

numberofinversions.

2’.

For

every pair of nodes ni,nj with C-j,

i,j 1,...,n, we determine the set

_Mi,j--Ti

71

(Tj’)

U

_Tj

71(Ti).

IfMi,

=0,

theoutputsYiand

yj are obviously unidirectionally independent

andtheoutputsYiandyj are calledgraphically

unidirectionally independent. If

Mi,j

0

we

havetocomputethe expression

Fi,

j; kaccording

to(i).

If for all k with

NkGMi,j,

Mi,j

we have

Fi,j;k

=0, the outputs_Yiandyjare unidirectionally

independent.

For

the circuit

_fe

of Fig. with the generalized

circuit graph’of Fig. 2,wehave

S1

--{N1,

N2, N3, N6,

N8),

S2

{N2,

N3, N6, N7,

N9

},

$3

={Ni,

N2, N4,

Ns,

NlO},

$4

--(N2,

Ns,

N6, N7,

Nil

},

$5

--{N4,

N12}

fromwhichweconcludethat

Pairs ofindependentoutputs can be determined in the following steps:

1. Consider the nodes n,...,nm of

f.

To

every

nodenj,j 1,...,m,weassignaset

Sj.

Thereby

a node Nk,

Nk

E

N

belongs to

_S

if thereexists

apathfrom

Nk

to

_n.

2. For every pair of nodes ni,nj with

i:/:

j,

i, j 1,..., n, wedetermine the set

Ri,

Sif)

Sj.

R1,5

S1

f’]$5

0,

R2,5

$2f-’l$5

0,

R4,5

$4I")$5

0,

andthe pairs ofoutputs_{Yl and}Ys,Y2 and Y5 and Y4 and_{Y5 are}graphicallyindependent.

(9)

are

T1

--{N1,N2,

N3,N6,

N8},T’

(,

T2

:{N2,

N3, N6,N7,

N9},

_T

{N3 }

T3 ={N,

N2, N4,

Ns,

_NlO},

_T

T4

--{N2,

Ns,

N6,N7,

Nil

},

_T

Ts

={N2},

_T’

{N4}.

For we have

Mi,j,i

-

j,i,j 1,...,5

M12

{N3},M13

},

_M14

O,M5

},

M23

},

M24

},

M25

},

M34

},

M35

{N4},

M45

}

andthepairs of output nodes

(nl,

n3),

(nl,

n4), (nl, ns), (n2, n3), (n2, n4),

(n2,

ns),

(n3,

n4)

and

_(n4,

_ns)

are graphically unidirectionally independent.

If we would like to determine not only the

graphically unidirectionally independent pairs of

outputs, the cases

_Mi,

y

(,

i.e.

M1,2

{N3}

and

M3,5--

{N4}

havetobeconsidered in more detail.

Since wehave dy dy2

F1,2;3

3 (x)

"z3

(x)(yl (x)

@

y2(x))

X3X4 0 and dy3 dy5

F3,5;4

z4

(x)"

z4

(x)(y3(x)

q)

ys(x))

0,

the outputsY3and Ysareunidirectionally indepen-dent and the _{outputs Y} _{and Y2} are not unidi-rectionallyindependent.

Now

wedescribe how

(maximal)

setsof

indepen-dent outputs can be determined.

To

this end we

draw a firstdependency graph

G=

(N

1,

gl).

The nodes N ofG are the outputs y,...,_Yn of the

considered circuit

_fe.

Two

nodesYi,

_Y

N are

con-nected by an edge ifthe pair of nodes is

(graphi-cally) independent.

Every

group of independent

outputscorrespondstoacompletesubgraphofG

1,

i.e. aclique ofG

1.

The determination of a complete

subgraphis astandardproblemofgraph theory.

In

a similar way, we determine sets of unidi-rectionally independent outputs.

We

drawasecond

dependency graph G2

N

2 _N2

Q..N_

V2)

Thenodes of

G

2_{are again}

the outputs Y1,. Ynof the considered

circuit

fe.

Two

nodesYi,YjEN2areconnectedbyan

edgeifthese nodes are (graphically)

unidirection-ally independent.

Every

group of unidirectionally

independent outputs corresponds to a complete subgraph

of__G

2,

i.e.aclique

of__G

2. In

thefollowing

example we restrict ourself to the graphically

independentand graphicallyunidirectionally

inde-pendentoutputs.

The graph G of graphically independent pairs

ofoutputsof

_fe

isgivenin Fig. 4. The threepossible

maximal complete subgraphs consist of the nodes

nl and ns, n2and n5 andn4 and

ns.

Fig. 5 shows

the graph G2 of the graphically unidirectionally

FIGURE4 Graphof independent outputs.

(10)

Yl

Y2

Y3

Y4

Y5

SCC1

Ull

U12

TRC

U1

U2

v21

v2

₂

Vl

₁

SCP

u22

FIGURE6 Self-checkingcircuitof theexampleof Fig. 1.

independent outputs of

_ft.

The maximal

com-plete subgraphs ofG2 consist ofthe sets ofnodes

{nl,

n4,

ns}, {nl,

n3,

n4}, {n2,

n3,

n4}, {n3,

n4,

ns}

and

{n2,

n4,

ns}.

We choose the set

_Y1

{n2,ns}

of graphically

independent outputsandthe set

_Y2

{nl,

n3,

n4}

of

graphically unidirectionally independent outputs.

Totheset

_Y1

{Y2,

Ys}

ofgraphicallyindependent

outputs a single parity bit vl,v

=--(Y2

(R)

_Ys)

is

added. Thuswe have

_Y1

{Y2,

Ys,Vl

}.

To the outputs Yl, Y3, Y4 ofthe group

Y2

two

additional outputs v21,v22 are added to form a

Beger

code with three information bits and two

control bits. _{All the additional outputs vl},v2 and

v22canbe jointly implemented. TheoutputsY2, Ys,

and V_l of the group

Y1

are checked by a self-checking parity checker SCP. The group

_Y2

is

checked by a self-checking

Berger

code checker

SCC

1. The outputs of the SCC and the SCPare

compacted by a self-checking two-rail-checker

TRC

asshowninFig. 6.

The resulting circuit is self-checking.

5.

EXPERIMENTAL RESULTS

Table showes the experimental results for the

MCNC

benchmarks.

Thefollowing abbreviationsareused:

inp: number of inputs

out: number ofoutputs

pgio: numberofpairs of graphically independent outputs

pguo: number of pairs of graphically

unidirection-allyindependent outputs

(11)

circuit inp out pgio

TABLE Experimental results

pguo pio puo go bB bP bT ao

2 3 4 cm138a 6 8 cu 14 11 33 cm162a 14 5 decod 5 16 27 ldd 9 19 29 apex7 49 37 361 z4ml 7 4 x2 10 7 3 c8 28 18 96 f51m 8 8 ttt2 24 21 105 vda 17 39 11 pml 16 13 63 5 6 7 8 28 28 54 33 54 2 3 4 4 120 27 120 79 61 171 522 379 555 12 3 6 3 14 4 15 4 152 96 152 2 5 7 4 116 128 148 7 17 169 343 14 68 69 74 2

puo: number of pairs of unidirectionally

inde-pendentoutputs

go: number of groups of independent and unidirectionally independentoutputs

bB:

number

of additional bits for

Berger

Codes

bP: number of additional paritybits

bT: total number of additional bits

(bT=

bB

₊

bP)

ao: additional

area

overhead in percent ofthe

area of the original circuit

The pairs of graphically independent outputs

pgio

(column

4)

and the pairs of graphically unidirectionally independent outputs pguo

(col-umn

5)

are determined by use of the modified

generalizedcircuit

_graph.

The pairs of independent

outputs pio

(column 6)

and the pairs of

unidi-rectionally independent outputs puo

(column 7)

are determined according to

(1)

and

(1’)

respec-tivelywhere thecorrespondingBoolean derivations

havetobe takenintoaccount.

The Boolean derivations in

(1)

and

(1’)

are

computed by use of the program system MIS

[17].

The corresponding Boolean functions are

repre-sented as

BDD’s.

Graphically

(ufiidirectionally)

independent outputs are always (unidirectionally) independent. Therefore, the number of pairs of (unidirectionally) independent outputs is always greater than or equal to the number of pairs of graphically (unidirectionally) independent outputs.

9 10 11 12 4 4 15 5 5 75 5 5 107 5 5 <1 5 5 31 3 10 13 119 3 3 62 2 3 5 85 6 6 156 6 7 55 4 5 9 79 26 26 60 3 4 88

The minimalnumberofmutuallydisjointgroups

of independent and unidirectionally independent

outputsgo are given in column 8.

Groups

of unidirectionally independent outputs

are monitored by

Berger

Codes. The number of

necessary additional bits bB is represented in

column 9.

Groups

of independent outputs are

checked by additional parity bits. Thenumber of additional parity bitsbPisgivenin column 10. The totalnumber ofcheck bitsbT (Bergercode bits and parity bits) is given in column 11 ofTable

I.

The

areaoverhead of the additional circuit

_fc

isshown

intherow12of Table. Theadditional circuit

_fca

was

sythesized byuseofthestructurally givencircuit

_fc

in the following way: If the outputs ofa group

Yi-- {Yi,..., Yihi}

are independent a single

addi-tional output vi ofthe paritybitis determinedby

connecting the outputs Yil,...,Yihi by

XOR-gates.

If the outputs of a group Yj

{yj,...,yjj}

are

unidirectionally independent the outputs

{yj,...,

yjj}

are connected to a counter of zeros

to determine the additional bits ofa

Berger

code. Then all the outputs of the circuit

_fea

are jointly

optimized by use of the standard MIS-algorithm

script.rugget.

The necessary computing time ona

SUN

Work-station Spark 10 including the determination of pairs of independent and unidirectionally indepen-dent outputs, the determination of maximal

(12)

circuit wasin therange of 0.33to3376.46seconds. The average additional area overhead is 71%.

6.

CONCLUSIONS

In

thispaperanewstructuredependentmethod for

the design ofself-checkingand self-testing combi-nationalcircuitswasproposed. Maximalgroupsof independentoutputsandunidirectionally indepen-dent outputs are determined.Itisshownhow pairs of (unidirectionally) independent outputs can

heuristically be determined by a simple

graph-theoretical algorithm. Maximal groups of

(unidi-rectionally) independentoutputscan becomputed

as cliques of a dependency graph, which is a

standard graph-theoretical problem.

A

single

parity bit is added toevery group ofindependent

outputs.

A

few additional outputs are added to

every group of unidirectionally independent out-puts in such a way that these groups of

unidi-rectionally independent outputs and the

corresponding additional outputs are elements of

aunidirectional errordetecting code. This method is explained in detail for a simple example. The

applicability of the proposed method is

demon-strated for the

MCNC

benchmarks.

Acknowledgment

The authors are very grateful to the reviewers of

thispaperfor theirhelpfulcomments.

References

[1] P. K. Lala, Fault Tolerant and Fault Testable Hardware

Design.PrenticeHall, Englewood-Cliffs,N.J.

[2] V. V.Sapozhnikov and V1.V.Sapozhnikov, Self-Checking

Checkers for Balanced Codes. Automation and Remote

Controlvol. 53,No3, part 1,321-348(1992).

[3] V. V.Saposhnikov and V1.V. Saposhnikov, Self-Checking

DiscreteCircuits(in russ.)Energoatomisdat,St.Petersburg (1992).

[4] S. K. GuptaandD. K.Pradhan,Can ConcuentCheckers

HelpBIST?, Proc.1992Intern.Test Conference,pp.140-150

(1992).

[5] R. M.Sedmak, Design for Self-Verification.AnApproach

for Dealing with Testability Problems in VLSI-based

Design. Proc. 1979 IEEE Test Conference, pp. 112-120

(1979).

[6] E. Fujiwara,N. Mutoand K. Matsuoka,ASelf-Testing

GroupParityPredictionChecker anditsUsefor

Built-in-Testing. IEEE Trans. Comp., vol. C-33, No 6, 578-583

(1984).

[7] T. R. N. RaoandE.Fujiwara,ErrorControl Coding for

Computer Systems,PrenticeHall(1989).

[8] E. S. Sogomonyan, Reliability of Self-Testing using

Functional Diagnosic Tools. Automation and Remote

Control, vol. 49,No 10,Part2, October 1988, pp.

1376-1380.

[9] E. S. Sogomonyan, Design of Built-In Self-Checking

MonitoringCircuitsforCombinational Devices.

Automa-tionandRemote Control, vol. 35,No 2, part 2, 280-289

(1974).

[10] E. Fujiwara, A Self-Testing Group Parity Prediction

Checker and its Use for Built-in Testing. Proc. 13th

Symposium Fault-Tolerant Computing, Milano, pp.

146-153(1983).

[11] E. S. SogomonyanandM.Goessel, Design of Self-Testing

andOn-lineFaultDetectionCombinational Circuits with

WeaklyIndependentOutputs. JETTA,4,267-281(1993).

[12] F.Y.BusabaandP. K.Lala, Self-CheckingCombinational

Circuit Design for Single and Unidirectional Multibit

Errors, JETTA, 5, 19-28(1994).

[13] J. M. Berger, A Note on Error Detecting Codes for

Asymmetric Channels.InformationandControl4, 68-73

(1991).

[14] D. A. Anderson and G. Metze, Design of Totally

Self-Checking Check Circuits for m-out-of-n Codes. IEEE

Trans. Comp.,vol.C-22,263-269(1973).

[15] M. A. Marouf and A. D. Friedman, Design of

Self-Checking Checkers for Berger-Codes. Proc. Int. Symp.

Fault-Tolerant Computing, 179-184(1978).

[16] S. Kundu and S. M. Reddy, Embedded Totally

Self-Checking Checkers.APracticalDesign.IEEEDesignand

TestofComputers,August1990,5-16.

[17] R. K.Brayton,R. Rudell, A.Sangiovanni-Vincentelli and

A. R. Wang, "MIS: Amulti-level logic optimization

prog-ram," IEEE Trans.Computer-AidedDesign,7,1062-1081.

Authors’ Biographies

Andrej

Morosow

received the M.S. degree in electricalenigneeringfrom the University of Rail-way Engineering, St. Petersburg, Russia, in 1992.

From

1992 to 1996 he was with Max-Planck-Society Fault Tolerant Computing

Group

at the UniversityPotsdam,

Germany.

Nowheis withthe

Computer

Science

Department

of the University of

Potsdam,

Germany,

where he is working toward

his Ph.D. degree. His research interest are the

design of self-checking and self-testing circuits. Prof. Valerij Saposhnikov received the M.S.

degree

(1963),

the Ph.D. degree

(1968)

and the

doctoral degree

(1982)

all in electrical engineering from the University of Railway Engineering,

(13)

St. Petersburg (formerly Leningrad), Russia.

In

1982 he became a professor, and in 1989 a vice president of this university. He published as an

author and coauthor about 250 scientific papers and 8 books in russian language in the field of synthesis, diagnosis, self-checking circuits and control systems for railway transportation. Since

1992 he is avisiting professor of the Max-Planck Fault TolerantComputing

Group

atthe University

of Potsdam,

Germany.

He is a member of the

Russian Transportation Academy and of the InternationalAcademyof Higher Education.

Prof. Vladimir Saposhnikov received his M.S.

degree

(1963),

the Ph.D. degree

(1969)

and the

doctoraldegree

(1984)

all in electrical engineering

from the University of Railway Engineering St.

Petersburg (formerly Leningrad), Russia. Since

1987 he is aprofessor and since 1991 the head of

adepartment. Since 1992 heis avisitingprofessor

of the Max-Planck Fault Tolerant Computing

Group

at the University of Potsdam,

Germany.

He

is the author and coauthor of about 300 scientific publications and 8 books in Russian

language. His research interests are synthesis and

diagnosis of discrete systems, self-checkingsystems

and fail-safe transportation systems. He is a

member of the Russian Transportation Academy

and of the International Academy of Higher Education.

Prof. Michael Goessel received theM.S.

Degree

(1965)

and the Ph.D.

Degree (1968),

both in

physics, from the University of

Jena, Germany

and the doctoral degree in

Computer

Science

(1971)

from the Technical University ofDresden,

Germany.

From 1966 to 1968 he was a research

assistent at the University of Leningrad.

From

1969 to 1991 he was with the Central Institute of Cybernetics

(ZKI)

of the Academy of Sciences, Berlin, of the formerly GDR.

In

1992 he was

appointed as the head of the Fault Tolerant Computing

Group

of the Max-Planck-Society at

the University of Potsdam,

Germany.

Since 1994 he is a full-timeprofessor of

Computer

Science at

the University of Potsdam,

Germany. He

is the

author andcoauthor of7 books,including "Error

DetectionCircuits",

(Goessel,

Graf, McGraw-Hill

1993)

and

"Memory

Architecture and Parallel

(14)

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