Rajeshwari Pandey, Member, IEEE, Neeta Pandey, Member, IEEE, and Rashika Anurag
Abstract—Continuous down scaling of CMOS device dimensions and increasing demand of battery portable applications has resulted in reduction of supply voltages. Reference circuits are widely used in analog, digital and mixed mode circuits. The reference generators are required to establish a DC voltage or current, stabilized over power supply voltage, process parameters and should have a well defined behavior with temperature. The system accuracy is highly dependent on the accuracy of voltage established by the DC reference voltage. The supply voltage in conventional reference circuits cannot be lowered below 1.2 volts. In literature various design techniques are classified to overcome these limitations. The accuracy of band gap reference voltage is crucial as it can severely limit the functionality of the system. Considerable work has been done to protect the reference voltage from variation in supply voltage and temperature.
This paper presents a classification study on reference generators using band gap techniques.
I. INTRODUCTION
Voltage reference circuits are usually required in many analog, digital and mixed signal circuits such as oscillator, PLLs, Data convertors and flash memory. These voltage reference circuits should exhibit little dependence on supply and process parameter and a well defined dependence on temperature.
Fig.1 shows the conventional band gap reference (BGR) circuit. The base emitter voltage of bipolar transistor exhibits a negative temperature coefficient. It is nearly complementary to absolute temp (CTAT) as it decreases linearly with temperature. If two transistors with collector current I0 operate at different emitter current densities (Is
andnIs) then difference between their base emitter voltages (ΔVBE) is proportional to absolute temperature (PTAT).
A PTAT voltage can be obtained as
where VT (=KT/q) is thermal voltage.
The principle of band gap circuit relies on, generating a fixed DC voltage with nominally zero temperature coefficient, by summing up a CTAT voltage with PTAT voltage.
Fig.1
In the circuit ΔVBE is the base emitter voltage difference between Q1 and Q2 and input voltages to amplifier are
controlled to be the same voltage, Vx = Vy, then the output voltage is given by
Rajeshwari Pandey is with Delhi Technological University, Bawana Road, Delhi 110042 India (e-mail: [email protected] ).
It is observed that the reference voltage is equal to band gap voltage of Si, Eg/q, extrapolated to absolute zero and
hence the name bandgap reference.
In recent years designing analog circuits at low supply voltage has become increasingly important due to great demand in battery powered portable devices and systems. As a result integrated circuits are required to be operated at low supply voltage. A major limitation in a conventional BGR is the supply voltage needed. It generates the output of around 1.2 V which makes the circuit unable to operate at lower supply voltage. This limitation is due to silicon bandgap voltage which is 1.2 V and the input common -mode range voltage of the amplifier.
To overcome these limitations various design techniques are proposed in the literature and can be broadly classified as:
1. Resistive Subdivision
2. Use of different active building blocks 3. Dynamic threshold MOS transistors(DTMOST) 4. Body driven techniques
5. Operation of MOSFETs in subthreshold
II. VARIOUS DESIGN TECHNIQUES A.RESISTIVE SUBDIVISION
Several low voltage BGR’s based on resistive sub division are reported [1],[4],[5],[6].Fig.2 shows the BGR proposed in[1] and reference voltage of this is given by
Required Vref can be obtained by adjusting the resistance ratio R4 and R2. The experimental results reveal that Vref is
515mV(mean value) ± 1 mV with supply voltage range 2.2 V to 4V at 27° and variation of ± 3mV around mean value for temperature ranging from 27° to 125°.
Fig.2
An improved circuit for reducing common- mode voltage is proposed in [4] with two stage op-amp having PMOS input differential pair. Resistors R1 and R2 are replaced with series equivalents R1D, R1U and R2D, R2U respectively.
The input common -mode voltage of the op-amp is reduced by introducing additional nodes Vax and Vbx.
Representing voltage drops across R1D and R2D respectively. This BGR can successfully operate with sub-1-v supply
with proper selection of R1D, R1U and R2D, R2U. The simulation results show mean reference voltage of about
559mV with different R3 values in temperature range 0-100° C.
B.USE OF DIFFERENT ACTIVE BUILDING BLOCKS
Fig.3
Where A1 and A2 are the emitter areas of Q1 and Q2 respectively. The first term is CTAT and 2nd term is PTAT
term. The minimum supply voltage can be expressed as
Min {VDD} = Vref +VSD sat
The value of Vref is typically 1.25 V while VSDsat range is about 0.1V- 0.3V. Therefore, the theoretical minimum
supply voltage is 1.4 V. A reduction in this limit can be achieved by resistive subdivision techniques [1], [4]. However as Vref is reduced, Min{VDD} will be limited by the input common- mode voltage range of the op-amp.
This limitation results from the fact that one of the op-amp input must be connected to one of the bipolar transistor to produce PTAT term. If NMOS differential input stage is used in the op-amp, the minimum input common –mode voltage is VTN +2VDS sat which will be higher than VEB for VTN >0.4V, since VEB can be as low as 0.45Vat a very
high temperature. Therefore usually a PMOS differential input stage is used and hence minimum supply voltage for practical CMOS BGR is given by
Thus a practical Min{VDD}will be about 1.8 V. A circuit wherein input differential stage is replaced by resistors
thus removing the op-amp input common –mode voltage constraint is proposed in [8] and is shown in Fig.4. These resistors are used to obtain PTAT current. It employs transimpedance amplifier (TIA) having high transimpedance gain and a very low input impedance with a fixed potential at both the input. Vref for the proposed circuit may be
obtained as:
Fig.4
The value of Vref can be changed by choosing different values of R1, R2, R3. The minimum supply voltage of BGR
is found to be equal to Max{ VSDsat2+ Max{VEB2}, |VT|P| + VDSsat + VSDsat}.The first term is the theoretical limit of
this BGR and second term is the minimum supply voltage of TIA [8].
Fig.5
The BGR voltage is given by
Another structure using OTA based on the topology [1] has been proposed in [10]. The two major differences are first, parasitic bipolar transistors are replaced by MOSFETs operating in weak inversion region. This lowers the voltage drop from about 0.6 volt to about 0.2 volt and hence operates at much lower supply voltages. Second being bulk current biasing for all PMOS to reduce the threshold voltage. In OTA design, to handle large variations of the input common-mode voltage, low VT NMOS transistors are used. Also bulk current biasing of PMOS in current
mirror is used to reduce the VT of these transistors. This increases the common -mode voltage swing.
C. Dynamic Threshold MOS Transistor (DTMOST)
Resistive subdivision is used to make bandgap smaller, but results in considerable area consumption. Bandgap can also be lowered by using electrostatic field. This is implemented by replacing normal diodes with MOS diodes that have gate, drain and substrate contacts connected together. These devices are dynamic threshold devices where every change in VGS causes a change in threshold voltage. The drain current is primarily determined by the VGS=
VWS, voltage across the source well junction which results in an exponential relation between VGS and drain
current ID. Since the P type gate is present over the N type well there is a built in voltage ØWG between the gate and
well. This built in voltage is divided over the gate oxide and the silicon due to capacitive subdivision. The drain current of a DTMOST is given by
Where Øb1 is drop in silicon due to ØWG and is given by
and is a function of ØGW and of a number of process dependent parameters. Thus the apparent material bandgap in
DTMOST is [2] Vgap apparent = Vgap,0 - Øb1.
The conventional diode has an exponential voltage to current relationship above 650mV while DTMOST configuration is exponential within a region from 100mV to 220mV.
The BGR circuit consists of a folded cascode op-amp implemented with DTMOST input stage. This allows operation of input stage at low supply voltages. The output stage of op-amp uses low voltage current mirrors. Correct operation of this BGR has been verified for supply voltages down to 0.7V. The variation of the output voltage Vref over temperature range (-20°C ≤ T≤100°C) is only 4.5mV.
technique[18]to overcome the above limitation. It consists of a two stage body- driven 1-V CMOS OPAMP, a bandgap core and a start up circuit. The op-amp provides a larger input common mode range without the use of low threshold voltage devices. The simulation results show that output voltage Vref has a variation of ±1.5mV from
mean output voltage of 592mV for a temperature range from 0-100°C with a supply voltage of 1V.
E.OPERATION IN SUBTHRESHOLD REGION
MOSFETs operated in sub threshold region are also used to generate the reference voltage independent of power supply and temperature. This results in reduction of chip area and power dissipation [14][15][21]. A constant reference current is generated in[15] and a thermal-independent grounded resistor is used to convert it to desired reference voltage . [19] proposes the circuit shown in Fig.6 which gives reference voltage as
Where α = (P11R3/P2R1), β=(( P10/P7) –N(P11/P2))(R3/R2) ζ ln(P9/P8) and P ≡ Weff/Leff
Fig.6
To obtain zero temperature coefficient the following condition must be satisfied:
Where
Gate source voltage of an NMOS (VGSn) which operates in weak inversion has a negative temperature coefficient. In
[16] the output of a PTAT core based on sub threshold MOSFETs is added with the VGSn to achieve independent of
temperature (IOAT) voltage reference. A current mirror is used for combining positive and negative temperature coefficients. The output voltage is given by
Where S8 and S9 are the aspect ratios of M8 and M9. Two circuits based on above concept are proposed in [16] and
can be classified as resistor based and all MOS based circuits respectively. Resistor based circuit is shown in Fig.7. CMOS voltage reference, which combines two linear voltages, one associated with PMOS threshold voltage (Vp)
and the other associated with NMOS threshold (Vn), to generate a reference voltage that is stable with temperature,
has also been reported in literature [17]. Both Vp and Vn have negative temperature coefficients but they differ in
Fig.7
[20] explores the opportunity of using Ge which is having a lower bandgap voltage than silicon. With the lower bandgap voltage of 660 mV, the germanium BGR uses lower supply voltages and thus results in a lower output reference voltage as compared to traditional Si BGR.
In most of the structures classified above, the difference between the drain voltages of output current mirror device and that of the BGR core results in a mismatch in the temperature dependency
of the current in these circuits. This results in the output voltage errors .To reduce errors, the output reference voltage is usually set close to the VBE of the BJT [22]. However, here as the output current mirror and output resistor form an open-loop configuration, the accuracy relies on voltage and layout matching alone [23]. Changes in drain voltage cause the temperature dependency of MOS current .This dependency is much higher in deep submicron CMOS technologies than that occurs in long channel devices. This makes it difficult to obtain an output voltage with an acceptable temperature coefficient using the open-loop mirror structure. [23] uses an additional circuit to match the drain voltages of the PMOS output device and the PMOS in the BGR core.
In the circuit proposed in [23] and shown in Fig.8 the transistor M3 is connected to a regulating device MR and an error amplifier U2 thus setting the drain voltage of M3 to that of M2. For the BGR core to operate correctly, the drain voltage of M2 must also match that of M1 which is achieved by a single-stage error amplifier U1. This structure ensures that the output current is correctly matched to the BGR core current the output reference voltage VREF is determined by setting the ratio between R3 and R1.
device technology continues to scale downward. In this paper a classification of voltage reference circuit is presented and two important design trends can be distinguished: One focusing on low power operations the other at high performance operations.
ACKNOWLEDGMENT
The authors would like to thank Dr. Debashis Dutta, Ministry of information Technology, Govt. of India for his invaluable suggestions.
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