Abstract :
A multilevel inverter with assumed equal dc sources, the multilevel fundamental switching scheme is used to control the needed power electronics switches. Also, a method is presented where switching angles are computed such that a desired fundamental sinusoidal voltage is produced while at the same time certain higher order harmonics are eliminated. In this paper PWM switching technique in three, four, five, six-level diode-clamped multilevel inverter (DCMLI) has been tested in Matlab/Simulink software packages. The DCMLI power circuit is drawn using the SIMULINK software package. The switching pattern generated using Matlab/Simulink file is linked with an inverter circuit through the Simcoupler module. Comparison of THD in various levels of diode clamped inverter has been carried out.
Keywords: Diode clamped inverter, multilevel inverter, PWM.
1. Introduction:
The term multilevel began with the three-level converter. Subsequently, several multilevel converter topologies have been developed [1]. However, the elementary concept of a multilevel converter to achieve higher power is to use a series of power semiconductor switches with several lower voltage dc sources to perform the power conversion by synthesizing a staircase voltage waveform [2]. Capacitors, batteries, and renewable energy voltage sources can be used as the multiple dc voltage sources [3]. The power switches aggregate these multiple dc sources in order to achieve high voltage at the output; however, the rated voltage of the power semiconductor switches depends only upon the rating of the dc voltage sources to which they are connected [4]. Controlled ac drives in the megawatt range are usually connected to the medium-voltage network. Now days, it is difficult to connect a single power semiconductor switch directly to medium voltage grids. For these reasons, a new family of multilevel inverters has emerged as the solution for working with higher voltage levels [5]. Some medium voltage motor drives and utility applications require medium voltage and megawatt power level. For a medium voltage grid, it is troublesome to connect only one power semiconductor switch directly [6]. Multilevel inverter overcome this trouble and give efficient power, due to that medium voltage grid can use for high voltage application [6].Numerous industrial applications have begun to require higher power apparatus in recent years. Some medium voltage motor drives and utility applications require medium voltage and megawatt power level. For a medium voltage grid, it is troublesome to connect only one power semiconductor switch directly [7]. In this paper started with operation of diode clamped inverter then simulations of three, four, five and six level diode clamped inverter, and using those results, conclusions are obtained regarding the harmonics minimization.
2. Operation of Diode clamped Inverter
Fig.1.Three level single phase DCI
The DC bus voltage is split into three voltage levels using two series connections of DC capacitors, C1 and C2. The voltage stress across each switching device is limited to Vdc through the clamping diodes D1 and D1’. It is
assumed that the total dc link voltage is Vdc and mid point is regulated at half of the dc link voltage, the voltage
across each capacitor is Vdc/2 (Vc1=Vc2=Vdc/2). In a three level diode clamped inverter, there are three different
possible switching states which apply the stair case voltage on output voltage relating to DC link capacitor voltage rate. A three-level diode-clamped inverter is shown in Fig.1. In this circuit, the dc-bus voltage is split into three levels by two series-connected bulk capacitors, C1 and C2. The middle point of the two capacitors n can be defined as the neutral point. The output voltage Van has three states: Vdc/2, 0, Vdc/2 and. For voltage
level Vdc/2, switches S1 and S2 need to be turned on; for –Vdc/2 , switches S1’ and S2’ need to be turned on; and
for the 0 level, S2 and S1’ need to be turned on. On the basis of this operation four, five and six level diode
clamped inverter has been studied and simulated.
3. Three Level Diode Clamped Inverter:
The three phase three level diode clamped inverter is as shown in fig.2. In 3 phase 3 level diode clamped inverter IGBT’s and diodes are used. Diodes are used to clamp the neutral point. Simulation has been carried out using resistive load.
Fig.2 Simulated schematic of 3 phase 3 level DCI
The output waveform of 3 phase 3 level DCI circuit is obtained and it is shown in fig.3. Here three levels of voltages are obtained according to the working of circuit. X-axis represents time in seconds and Y-axis represents voltage levels.
Fig.3. Output voltage waveforms of 3 phase 3 level DCI.
Fig.3. shows three levels at the output that is first level is 100 volt, second level is 0volt & third level is -100volt.
4. Four Level Diode Clamped Inverter:
The three phase four level diode clamped inverter as shown in fig.4. In 3 phase 4 level diode clamped inverter IGBT’s and diodes are used. Diodes are used to clamp the neutral point. Simulation has been carried out using resistive load. Instead of dc link capacitor directly the dc source is connected as the work has to be carried out on balancing of dc link capacitor.
Fig.4 Simulated schematic of 3 phase 4 level DCI
Fig.5. Output voltage waveform of 3 phase 4 Level DCI
In this output waveforms the four levels are obtained but no symmetry is found because zero level is absent. First level is 100V, second level is 200V, third level is -100V fourth level is -200V. Now comparing the waveforms of fig.3 and fig.5, it is observed that the waveforms of fig.5 are more sinusoidal than the waveforms of fig.3, so the four level is better than the three level.
5. Five Level Diode Clamped Inverter:
The three phase five level diode clamped inverter is as shown in fig.6. In 3 phase 5 level diode clamped inverter IGBT’s and diodes are used. Diodes are used to clamp the neutral point. Simulation is carried out using resistive load. Instead of dc link capacitor directly the dc source is connected as the work has to be carried out on balancing of dc link capacitor. Here as the level of inverter increases the number of switches that is IGBT’s, diodes, and dc sources used are increases.
Fig.6 Simulated schematic of 3 phase 5 level DCI
The output waveform of 3 phase 5 level DCI circuit is obtained and it is shown in fig.7.Here five levels of voltages are obtained according to the working of circuit. X-axis represents time in seconds and Y-axis represents voltage levels.
Fig.7.Output voltage waveform of 3 phase 5 Level DCI
Fig.7 shows output of 3 phase 5 level diode clamped inverter. From the voltage waveform it is seen that five levels of voltages are obtained. First level is 0V, second level is 100V, third level is 200V, fourth level is -100V and fifth level is -200V. Now comparing the waveforms of fig3,5 and 7 it is observed that the waveforms obtained in 3 phase 5 level DCI is better than the waveforms obtained in three and four level diode clamped inverter.
6. Six Level Diode Clamped Inverter:
The three phase six level diode clamped inverter is as shown in fig.8. In 3 phase 6 level diode clamped inverter IGBT’s and diodes are used. Diodes are used to clamp the neutral point. Simulation has been carried out using resistive load. Instead of dc link capacitor directly the dc source has been connected as the work is to be carried out on balancing of dc link capacitor. Here the level of inverter increases the number of switches that is IGBT’s, diodes, and dc sources are also increases.
Fig.8 Simulated schematic of 3 phase 6 level DCI
Fig.9 Output voltage waveform of 3 Phase 6 Level DCI
According to the output waveforms the six levels are obtained but it is not symmetrical. First level is 0V, second level is 100V, third level is 200V, fourth level is -100V, fifth level is -200V and sixth level is -300V. Now comparing waveforms of fig.3,5,7 and 9 it is observed that as the level increases the output become more sinusoidal and hence the more pure signal.
7. THD Analysis of Three, Four, Five AndSix Level Diode Clamped Inverter:
Some harmonics levels in every levels of diode clamped inverter during this study are shown in table-1.
Table-1: DC component, 3rd, 5th, and 7th levels in DCI:
Table-1 shows the analysis of dc component for 3rd, 5th, and 7th order harmonics in diode clamped inverter. From these results it is observed that increase in levels of inverter give better output and as the levels are increased the harmonics are minimized so that the total harmonic distortion is minimized. Total harmonic distortion of various levels of diode clamped inverter has been presented in table-2.
Table.2: THD of different levels of DCI:
Levels of Diode Clamped Inverter (DCI) Total Harmonic Distortion (THD) %
Three 28.62 Four 19.25 Five 13.62 Six 6.24
A study of Table-2 reveals that as the level of DCI is increased the THD values are decreased. It is also observed that dc component is present in the output of even level DCI where as the dc component is absent in odd levels. So, odd level inverters are better and preferred mostly in Industry.
8. Conclusions:
The Diode clamped inverter topology used for multilevel inverter for minimizing the THD. Here simulation has been carried out for three, four, five, and six level multilevel inverter using PWM switching technique. It is concluded that as the number of level in multilevel inverter is increased the THD is minimized.
9. Future Work:
PWM switching technique can’t remove the lower order harmonics but Space Vector Modulation removes the lower order harmonics. Due to the removal of lower order harmonics the signal become pure and efficiency and
Levels of DCI
DC component(V) 3rd Harmonics
(V)
5th Harmonics (V)
7th harmonics (V)
Three 0 16 5.2 1.9
Four 2 7 3.8 2.4
Five 0.1 0.3 0.2 0.18
Six 29 0.19 0.12 0.09
