2005 Sep AdvancedPkg

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Underfill Voids

Eliminating

X-ray

Inspection

MEMS Update

Temperature

Sensors

2005 APA

Recognition

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SEPTEMBER

SEPTEMBER 2 2

THE

THE INTERN TION INTERN TION L L M M G G ZINE ZINE FOR FOR ELECTRONIC ELECTRONIC P P CK CK GING GING PPLIC TIONSPPLIC TIONS

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Heavy Wire Bonder

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FiFinne e WWirire e BBonondederr GGoold ld BBalall l BBonondderer

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Advanced Advanced

Packaging

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Packaging

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Heavy Wire Bonder

Heavy Wire Bonder 66000 G5

FiFinne e WWirire e BBonondederr GGoold ld BBalall l BBonondderer

Innovative Technology Defines The

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PUBLISHER

EDITOR-IN-CHIEF

ASSISTANT EDITOR

SILICON VALLEY OFFICE TECHNICAL EDITOR EDITORIAL OFFICES ART DIRECTOR ILLUSTRATOR PRODUCTION MANAGER CIRCULATION MANAGER

SENIOR VICE PRESIDENT COMMUNICATIONS AND OPTOELECTRONICS GROUP DIRECTOR, ATD AUDIENCE DEVELOPMENT ATD PRODUCTION DIRECTOR GROUP ART DIRECTOR ATD BUYERS GUIDE DIRECTOR CORPORATE OFFICES

CORPORATE OFFICERS CHAIRMAN PRESIDENT AND CEO CHIEF FINANCIAL OFFICER

Jay Regan 603-891-9126 [email protected] Gail B. Flower 603-891-9395 Fax: 603-891-9328 [email protected] Lee Mather 603-891-9176 Fax: 603-891-9328 [email protected] Julia Goldstein 408-376-3987 [email protected] Communications and Optoelectronics Group 98 Spit Brook Road Nashua, NH 03062-5737 Kelli Paquette-Mylchreest Chris Hipp Sheila Ward Michelle McKeon 603-891-9351 [email protected] David Janoff Gloria S. Adams Mari Rodriguez Meg Fuschetti Judy Simers

1421 South Sheridan Road, Tulsa, OK 74112;

918-835-3161

Frank T. Lauinger Robert F. Biolchini Mark Wilmoth

Advanced Packaging magazine is published by PennWell Corporation. Reproduction of text and illustrations is not allowed without express

written permission. Opinions expressed by authors are not necessarily those of the publisher, and this publication can accept no responsibility in connection with any liability which might develop as a result of articles published.

2 ADVANCED PACKAGING September 2005 www.apmag.com

®

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   Advanced

Packaging

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There’s a reason people are getting excited. For over 20 years Newport has set the industry standard for complex die bonding solutions. Today we have taken it another step forward with the introduction of the next generation assembly work cell, the new MRSI-M5™. Flexible by design, the MRSI-M5 is the right choice for accuracy, speed and reliability.

The MRSI-M5 system has a large work area and is the best solu tion for a variety of die bonding interconnect technologies including eutectic, epoxy die attach and various flip chip processes. And, with Newport you can rest assured that you are working with an industry leader who delivers global support, process experience and manufacturing expertise. To see what all the excitement is about, visit www.newport.com/workcell18 or call 978.667.9449.

Some people just can’t wait to see the new

MRSI-M5

™

_{assembly work cell.}

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The Carsem MLP Advantage

Carsem’s comprehensive selection of cost-effective

MLP solutions gives you the crucial advantage you

need for today’s demanding applications.

Carsem’s MLP (Micro Leadframe Package) is ideal for the demanding applications requiring near chip-size packages with superior thermal-electrical performance. Our high-density leadframe design concepts, high throughput singulation methods, and innovative technologies allow our MLP to meet the most stringent MSL-1, Pb-free and green requirements, while delivering the most cost-effective solutions you could need. Our patented FCOL™ (Flip Chip on Lead) and COL (Chip on Lead) options provide even greater utilization of package space and enhanced performance for your designs. Carsem also offers turnkey services including RF testing.

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ONLINE

w w w . a p m a g . c o m

INDUSTRY NEWS UPDATES . NEW PRODUCT HIGHLIGHTS . EDITORIAL COMMENTARY . SEARCHABLE ARTICLE ARCHIVES INDUSTRY ASSOCIATION LINKS . CALENDAR OF EVENTS . TRADE SHOW NEWS . LEAD-FREE WEBINARS

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T H E b a c k - e n d P R O C E S S S E P T E M B E R 2 0 0 5

On The Cover

Voids or air gaps in underfill are a common problem across underfill applications, from the smallest die on flex to the largest BGA. The

consequences of having voids in underfilled parts depend on the package design and use model. Courtesy of Asymtek.

18

A close-up of plug-and-play technology that links the application to the calibration lab. A top view of a thermoplastic cavity package.

22

A diagram of a typical X-ray system for industrial inspection.

24 FEATURES

14

Troubleshooting Underfill Void Elimination

Methods for Gaining Reliability in Underfill Applications

BY ALAN LEWIS

18

IEEE 1451.4

Facilitating Temperature Sensor Success

BY CHRIS SEYMOUR

20

MEMS Packaging Update

Providing a Foundation for Future Packaging Advancements

BY KEN GILLEO

24

Building on a Basic X-ray Inspection Platform

Configuring an X-ray Inspection System

BY UDO E. FRANK

DEPARTMENTS

7

Editorial

BY GAIL FLOWER

8

In the News

29

Advanced Packaging Awards

Special Section

51

IMAPS 2005 Product Preview

55

Advertiser Index

56

Editorial Board

BY JOSEPH FJELSTAD

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Precious moments. Shared when you’re not there. All because smaller, more advanced components can

rely on packaging that’s durable in even the most demanding circuitry. That’s where you’ll find NuSil. Our customizable, low-outgassing packaging materials are helping opto-electronic systems stay contaminant-free under stressful, heated conditions. While your needs might be very different, from

large batches to small, you can count on NuSil to deliver precise, custom formulations and the most complete line of encapsulants, under-fills and die-attach adhesives available. All backed by more than 25 years of packaging materials expertise. What? When? Where? If it’s NuSil, it’s no problem.

Flight delayed.

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NuSil Technology.

What’s your challenge?

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Europe +33 (0)4 92 96 93 31

US 805/684-8780

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Editorial

G A I L F L O W E R

www.apmag.com September 2005 ADVANCED PACKAGING 7

EDITORIAL ADVISORY BOARD

Daniel Baldwin, Ph.D. Engent Corp. Jeffrey C. Demmin Tessera Technologies Joseph Fjelstad SiliconPipe Inc. Nasser Grayeli, Ph.D. Intel Corp. Bruce Hueners Palomar Technologies R. Wayne Johnson, Ph.D. Auburn University Stephen Kay Ultratech Inc. George Ri ley, Ph.D. FlipChips Dot Com Michael Steidl Amkor Technology Inc.

Rao R. Tummala, Ph.D. Georgia Institute of Technology Jim Walker

Gartner-Dataquest

S

omeone once said that to do the same thing over and over while expecting a different result is the definition of insan-ity. I thought of this while attend-ing SEMICON West on July 12 – 14 in San Francisco. During each interview with company leaders, each review of new products, and each technical session, I looked for what was innovative and a source for new ideas. Original thinkers are keeping the back-end ahead of the recovery curve in the electronics marketplace, and I was on a mission to talk to a few creative leaders.

Tien Wu, Ph.D., Advanced Semiconductor Engineering, Inc.’s (ASE) president, Americas/ Europe, presented a fresh perspec-tive on mostly everything involv-ing advanced packages. His back-ground — a BSCE degree from Taiwan University and a MS and Ph.D. in mechanical engineering from the University of Pennsylva-nia — fits his career choices. Prior to joining ASE, Wu held several management positions at IBM, including R&D, process develop-ment, manufacturing, application and ASIC design, marketing, and sales in the U.S., Europe, and the Asia-Pacific region.

How was ASE’s growth out-standing this year? SEMI’s mid-year capital equipment consensus forecast for the semiconductor industry showed a 12% decline from 2004 figures, ending at a predicted $32.6 billion in sales for 2005. SEMI members antic-ipated cautious spending this year, as the expanded capacity in 2004 was absorbed. Respondents to SEMI’s survey said that the market would grow at a single-digit rate in 2006 and reach $44.3 billion in 2008. ASE is gaining market share among SATS pro- viders, and their growth shows double digits this year, outpac-ing competitors.

Wu sees a tightening of capac-ity in back-end processing, and expects 2006 to be especially fruitful for this segment of the market. Back-end is leading the industry, and ASE provides back-end services. But there’s more to it than being in the right market segment. There are lots of reasons for ASE’s success, ac-cording to Wu, including: · Flexibility of package

assem-bly services, including bump-ing, bondbump-ing, testbump-ing, supplying materials, and providing turn-key or stand-alone assistance. · Right investments for future

growth.

· Willingness to meet present demands or perceive future customer demands.

If a customer wants complete-ly free, ASE provides lead-free packages. Cost control is one of the biggest problems with lead-free, according to Wu. The cheapest material that works well is what a customer will use. How-ever, at present, there are no reli-able standards of material choices and no recipe. Each bill of mate-rials is different for each OEM. Eventually, lead-free will evolve in the industry, but it will take a few standards and verification of materials used.

We asked Wu where he saw the boundary between the front-and back-end. He said that it was much more determined by busi-ness than by technology. “Mon-ey, not processes, determines the difference between the front- and back-end,” he added. That will be another topic for a future article in Advanced Packaging .

Editor-in-Chief

A Breath of Fresh Air

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8 _{ADVANCED PACKAGING} _{September 2005} _{www.apmag.com}

NEWS

I N T H E

Intel to Build 300-mm Wafer Factory

in Arizona

SANTA CLARA, CALIF. —_{Intel Corp. plans}

to build a new 300-mm wafer fabrica-tion facility at its Chandler, Ariz. site, and the $3 billion project’s construction is set to begin immediately. Designated Fab 32, the new factory will begin mi-croprocessor production in late 2007 on 45-nm process technology. “This invest-ment positions our manufacturing net-work for future growth to support our platform initiatives, and will give us ad-ditional supply flexibility across a range of products,” states Paul Otellini, Intel’s CEO. Once completed, Fab 32 will be-come Intel’s sixth 300-mm wafer facility, and the structure will be about 1 million sq. ft. — 184,000 sq. ft. of which will be cleanroom space.

300-mm wafer manufacturing increas-es lower-cost semiconductor production ability when compared to 200-mm wa-fers. Total silicon surface area of a 300-mm wafer is 225%, or more than twice that of a 200-mm wafer, and the number of printed die increases to 240%. Larg-er wafLarg-ers lowLarg-er production cost pLarg-er chip while eliminating overall use of resources — 300-mm wafer manufacturing will use

40% less energy and water per chip than a 200-mm wafer factory.

Intel also plans to invest $105 million to convert an existing, inactive wafer fab in New Mexico to a component tempo-rary test facility. The project will provide additional test capacity to the company’s factory network for the next 2 years, re-sulting in an additional 300 jobs at the New Mexico site during that time. AP

SEMI Appoints New Board Chair,

Board Member

SAN FRANCISCO, CALIF. — _{SEMI has}

ap-pointed Ed Segal, senior advisor to Me-tron Technology, as chairman of SEMI’s International Board of Directors. Segal succeeds Tetsuro (Terry) Higashi, chair-man and CEO of Tokyo Electron Ltd., who served as chairman for the past year. Also appointed as the Board’s new-est member is Michael Splinter, president and CEO of Applied Materials. Archie Hwang, chairman and CEO of Hermes Epitek, succeeds Segal as vice chairman of the board.

Segal served as CEO of Metron from July 1995 until its acquisition by Applied Materials in December 2004. Prior to join-ing Metron, he served as president and CEO of Transpacific Technology Corp., a company he founded in 1982, which later merged with Metron. “SEMI is a unique global trade organization serving the semiconductor equipment and materi-als industry. In a period when the needs of members are shifting, I am pleased to have the opportunity to serve as chairman of the organization,” says Segal. AP

SMT China

_{International}

Conference Call for Papers

SHANGHAI, CHINA — _{PennWell and}

China Electronics Appliance Corpo-ration (CEAC) will sponsor the 2005 SMT China International Confer-ence on “Emerging Technologies and Lead-free Challenges,” November 21-22, 2005. This 3rd annual conference will take place at the Shanghai Inter-national Convention Center, Shang-hai, China, in conjunction with the CEAC’s 66th China Electronic Fair (CEF).SMT and SMT China maga-zines, sister publications to Advanced Packaging , announce a call for papers for this conference on topics such as high-density, fine-pitch placement; equipment modular design; process optimization programming; 0201 and 01005 components; chip scale, BGA, flip chip, and 3-D interconnection; nanotechnology; and MEMS; as well as several other SMT, emerging tech-nology, and modern assembly topics. Papers from environmental man-agers and technical experts are sought on relevant subjects. For a complete list of topics, and for the submis-sion form, please visit www.smtmag. com. Abstracts should be 300 words in length and include an attached ab-stract submission form and a brief biography. The deadline for abstract submission is September 25, 2005. Presenters will be allotted 40-min-ute time slots for their presentation and discussion. Simultaneous Man-darin/English interpretation will be provided. Some papers may be grouped together in a forum or pan-el discussion. Speakers will receive discounted admission to the con-ference, including a copy of pro-ceedings, and any refreshments and luncheon. For more information on the event, please e-mail Gail Flower at [email protected]; or Charlie Zeng at [email protected]. AP

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A

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& M

A N U F A C T U R I N G

Lead-Free Webinar Series

www.apmag.com/webcasts

Participate in the discussion.

Talk to the experts.

Register

today!

Wednesday, October 11

TH

_{, 12:00 Noon (Central)}

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BY JULIA GOLDSTEIN

SAN FRANCISCO, CALIF. —_Many

compa-nies were eager to share their technol-ogy and business news with the editors at Advanced Packaging . Here is some of what we saw:

Test sockets. Kulicke & Soffa (K&S)

introduced a new test socket technol-ogy last year that replaces traditional spring-loaded pins with a photolithog-raphy-based process. Flexible metal leads are used as the contacts, providing low contact force to minimize pad or bump damage. Oded Lendner, senior VP of

Package Test, explained that K&S now has a product based on this technology, called Quatrix, which is being tested by customers and is expected to go into pro-duction at the end of the year. Contactor life has been tested up to 2.5 million cy-cles, and will be specified at one million cycles for production. Standard metal-lization is Au over Ni, with a Pd-based alloy as an option for probing lead-free solder bumps. In an effort to improve time-to-market for their standard prod-ucts, K&S introduced web-based socket selection software that enables custom-ers to input specifications for BGA test sockets and receive a detailed footprint diagram and quote within 24 hours. Gold Technologies has a new product for test-ing lead-free packages that is based on their spring-loaded Au-plated probes, but includes a proprietary coating on the pins, as well as higher spring force. They have also introduced a socket lid design that can accommodate a range of package heights.

Wafer Dicing. Laser dicing technol-ogies are coming to the forefront. One new player in the semiconductor space will be New Wave Research. They in-troduced a compact laser scribing sys-tem for 2- and 3-in. sapphire wafers six months ago, which is now used for high- volume production by customers in the LED market. A new system for silicon wafer dicing that can accommodate up to 12-in. wafers is in development and expected to be released in a little over a year. Synova was showcasing their wa-ter jet-based laser system. Guiding the laser beam down a 25- to 50-µm-wide water jet allows a much larger working distance than conventional laser dicing methods, and the water automatically cools the area being cut, eliminating the heat-affected zone. CEO Bernold Richer-zhagen noted that customers are using the system to cut Si, GaAs, and SiC wa-fers, as well as to remove edge damage from thinned wafers after backgrinding. Synova’s next focus will be on package dicing, where the variety of materials to

NEWS

I N T H E

News from SEMICON West

continued on page 13

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0509AP_11 11

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     

    

Ultratech

          



     



   

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      

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    

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      

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       



                                                  _{}

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F F

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be cut poses many challenges.

Materials.Honeywell discussed their wafer-thinning materials, announced in April as the first new product line from their Chandler, Ariz. manufacturing fa-cility. By using a bulk etch, a stress relief etch, and a texture etch to enhance ad-hesion, they are able to completely re-place backgrinding and the wafer dam-age that goes along with it.

Polysciences, Inc. has been manufac-turing encapsulants and adhesives for OEM customers for decades, but this is the first year they exhibited at SEMI-CON. One of their products is an en-capsulant that is dispensed in a fine line over wire bonds to lock the wires in place. It effectively halves the length of the long wires used in stacked pack-ages. The encapsulant flows down to un-derlying wires, but does not touch the substrate. Standard overmolding ma-terials and processes can then be used with minimal risk of wire sweep.

China or Mexico? Manufacturing in China has been a hot topic in re-cent years, with much of the emphasis on reducing manufacturing costs. Key-note speaker Tien Wu, President of ASE Americas & Europe, gave an interesting viewpoint. He said, “Why you want to go to China [is] to rule the world,” not to save 20%, but to be well-positioned to sell products to the Chinese. He also not-ed that the emergence of China could be considered as a “black hole” draining re-sources from the U.S. or as a new growth engine driving the semiconductor indus-try. Tien’s advice to companies consid-ering expanding into China is not to go ahead if their only reason is to trim labor costs. Labor costs are rising in China, as Scott Kulicke noted during K&S’s Press Luncheon. High employee turnover, as much as 25%, is a problem, and some technical and managerial expertise is not available in China. Hiring workers from Taiwan and Singapore to fill the gaps in-creases costs. Still, K&S continues to shift more of its manufacturing to China, and Kulicke said that 90% of its wire bonder sales are to Asian customers.

Ron Jones, co-founder of Silicon Bor-der, is looking to greatly expand

man-ufacturing in Mexico and recently announced groundbreaking on a billion-dollar industrial and educational com-plex in Mexicali, Mexico, just south of the U.S. border. Silicon Border has hired two engineering firms, one American and one Mexican, to design and build the infrastructure and provide support to tenants building manufacturing fa-cilities. Jones is in negotiations with

po-tential tenants — IDMs from the U.S., Europe, and Asia — and expects to sign letters of intent by this fall. The long-term goal is to have manufacturing facilities covering all steps of semiconductor fab-rication and assembly, providing a com-plete supply chain in North America. If the first tenants are successful, it is likely more will come and make Silicon Border a viable alternative to China. AP

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www.apmag.com September 2005 ADVANCED PACKAGING 13

NEWS

I N T H E

continued from page 10

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C O V E R S T O R Y

V

oids or air gaps in underfill are a common problem across underfill applications, from the smallest die on flex to the largest BGA. The consequences of having voids in underfilled parts depend on the package design and use model. Voids typically result in a loss of reliability. This article explores strategies for troubleshooting void problems.

Detecting Voids

If you have determined there is a voiding problem, you prob-ably already have a method of detecting the voids; however, different methods can be useful for troubleshooting. Three of the most common methods for detecting voids are the use of a glass die substrate, ultrasonic imaging, and destructive testing of a cross section or breaking the die off the part.

Using a glass die or substrate can be helpful. This method provides instant feedback during testing and can be used to help understand flow patterns to optimize underfill speed. Us-ing underfill materials of different colors can also help visual-ize the flow. The disadvantage of this method is that flow and voiding behavior may be slightly different for glass parts than

actual production parts.

Ultrasonic acoustic imaging is a powerful tool. It allows the user to detect voids in the underfill material on the actual pro-duction part before or after cure. The size of the void to be de-tected can be limited depending on the package and equipment used, so there is a need to check with the equipment makers to understand what size void can be detected. These tools are also useful in reliability testing to detect delaminating and intercon-nect failures. Figure 1 shows an image of a void in an underfilled package taken with an acoustic microscope.

Destructive testing uses a cross-section saw or breaks the die or package away from the underfill. These methods can be use-ful to better understand the three-dimensional shape and po-sition of the void. The primary disadvantage of this method is that it cannot be used on uncured parts.

Causes of Voids

There are several potential root causes of voids. Describing them and their root causes helps devise tests to troubleshoot them. Some causes include:

• Flow pattern voids. There are several sub-categories here, but all of these voids occur during the time the material is flowing

un-BY ALAN LEWIS

T R O U B L E S H O O T I N G

METHODS FOR GAINING RELIABILITY IN UNDERFILL APPLICATIONS

UNDERFILL

V O I D E L I M I N A T I O N

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www.apmag.com

www.apmag.com September September 20052005 ADVANCED PACKAGINGADVANCED PACKAGING 1515

C O V E R S T O R Y

der the die or package. The leading edge

of the wave front traps a pocket of air.

•

• Mois Moisture ture voidsvoids. This type of void occurs. This type of void occurs

during curing when moisture from the

substrate outgases. This commonly

oc-curs in organic substrates.

curs in organic substrates.

•

•Voids caused by bubbles in the fluid Voids caused by bubbles in the fluid . This. This

is rare in fluids that materials suppliers

packaged, as most suppliers are

care-ful about packaging materials air-free.

ful about packaging materials air-free.

However, mishandling the fluid or

re-packaging after receipt from the suppler

packaging after receipt from the suppler

can introduce bubbles. In some cases,

suppliers provide samples or

experi-mental fluids that may not be properly

mental fluids that may not be properly

de-gassed. If not configured properly,

some automated dispensing equipment

can also induce bubbles in the fluid path

during dispense.

•

•Contamination voidsContamination voids. Contamination of. Contamination of

excess flux

excess flux or other sources of contami-or other sources of

contami-nation can occur in a variety of ways.

nation can occur in a variety of ways.

Void Characteristics

Void characteristics can help match them

up with their root causes. These include:

• Shape — Are the voids round or some

other shape?

•

• Size — VSize — Voids are usually describeoids are usually described as thed as the

area they cover in the plane of the die.

• Frequenc

• Frequency — Do you get about one voy — Do you get about one voidid

per 10 parts, or 10 voids per part? Do

voi

voids ds occuoccur r duriduring ng specispecific fic timetimes, s, all all thethe

time, or randomly?

• Location — Do

• Location — Do the voids appear in onethe voids appear in one

place of the die or randomly? Do they

appear attached to interconnect bumps?

What is the relationship of the void to

the dispense pattern?

Test Strategies

The first step is to determine if the voids

occur before or after curing. This can be

helpful in eliminating some root causes. If

the voids are not present after dispensing,

but are present after curing, f

but are present after curing, flow patternlow pattern

voids

voids, or voids caused by bubb, or voids caused by bubbles in theles in the

fluid, can be eliminated as a root cause.

At this point, it would be good to look

for moisture problems, contamination

problems, some source of outgassing

dur-ing cure, or problems with cure profiles.

ing cure, or problems with cure profiles.

Most underfill materials are designed to

shrink during cure

shrink during cure to create compressiveto create compressive

stress on the interconnect bumps to

im-prove reliability

prove reliability. This . This shrinking can giveshrinking can give

any outgassing source the ability to

cre-ate a void. If the voids are present with

ate a void. If the voids are present with

the same characteristics before and

af-ter cure, it is a

ter cure, it is a good indication that somegood indication that some

flow pattern during the underfill process

caused the void. If the number of voids

changes after cure, there could be more

than one root cause. In some cases,

con-tamination can cause two different types

tamination can cause two different types

of voids; they can create an obstruction

during flow, then outgas during cure.

Flow-pattern Voids

Tw

Two or more flow o or more flow fronts meeting to trapfronts meeting to trap

a pocket of air cause flow-pattern voids.

One cause of this can be the dispense

pattern. Dispensing on multiple sides of

a BGA or die can improve the speed of

the flow, but increases the probability of

trapping a void. Experimentation with

various dispense

various dispense patterpatterns or ns or parts withparts with

a quartz die or transparent substrate is

the most direct method of

understand-ing how the voids are formed and how

ing how the voids are formed and how toto

eliminate them. The use of underfill

ma-terials with different die colors for

terials with different die colors for

var-ious dispense passes (Figure 2) can be a

ious dispense passes (Figure 2) can be a

good tool to visualize flow.

Temperature can affect the flow front

of the material. Temperature variations

on the part can also affect material

on the part can also affect material cross-

cross-linking during flow, speed of flow, and

linking during flow, speed of flow, and

flow speed. Therefore, it is prudent to

consider this variable in testing.

Often, multiple dispense passes are

used to reduce fillet size, but can also

in-crease the probability of trapping voids if

crease the probability of trapping voids if

timing between the passes is

timing between the passes is not carefullynot carefully

planned and controlled. The use of jetting

Figure 1.

Figure 1.Image taken with acousticImage taken with acoustic

tomograph shows void in underfilled package.

Photo courtesy of Hitachi Kenki FineTech.

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8/26/05 12:29:47 8/26/05 12:29:47 PMPM

Advanced Advanced

Packaging

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16

16 _{ADVANCED PACKAGING}_{ADVANCED PACKAGING} _September_September₂₀₀₅₂₀₀₅ _{www.apmag.com}_{www.apmag.com}

C O V E R S T O R Y

technology, instead of needle dispensing,

to control fillet size can help reduce the

number of passes.

number of passes.11_{Figure 3 shows jet dis-}_{Figure 3 shows jet}

dis-pensing of underfill.

pensing of underfill.

Material flowing to other board

fea-tures (passive components or vias),

tures (passive components or vias),

leav-ing the underfill material short, can also

ing the underfill material short, can also

cause flow-pattern voids. The use of

jet-ting technology can help control the

ting technology can help control the

placement of the underfill fluid.

Moisture Voids

Moisture in the substrate can outgas

dur-ing cure, creatdur-ing a void durdur-ing the cure

ing cure, creating a void during the cure

process. These voids are often random in

placement and can have finger- or

placement and can have finger- or snake-

snake-like shapes. They usually are seen in

like shapes. They usually are seen in

pack-ages using organic substrates.

ages using organic substrates.

To test if voids are caused by

mois-ture, one can pre-bake the parts for

ture, one can pre-bake the parts for

sev-eral hours at temperatures above 100°C,

eral hours at temperatures above 100°C,

then dispense immediately on the parts.

Once it has been established

Once it has been established that moisturethat moisture

is the root cause, further testing to

estab-lish optimal pre-bake times, temperatures,

lish optimal pre-bake times, temperatures,

and storage protoco

and storage protocols can be ls can be designed. Adesigned. A

good metric for water content is to track

weight gain of a part

weight gain of a part with a precision an-with a precision

an-alytic balance.

alytic balance.

Note that some flux contamination

issues can be remedied with a pre-bake

procedure and act like moisture-induced

problems. It is easy to test for the

differ-ence. Moistuinduced problems will

ence. Moistuinduced problems will

re-cur if the part is exposed to humidity; flux

cur if the part is exposed to humidity; flux

contamination prob

contamination problems will lems will not.not.

Contaminat

Contamination issues caused ion issues caused by excessby excess

flux often create irregular or random flow

variatio

variations, ns, particularly at particularly at the the interintercon-

con-nect bumps. If the voids that are

nect bumps. If the voids that are

occur-ring duoccur-ring flow show this characteristic,

ring during flow show this characteristic,

it would be prudent to investigate

clean-ing or sources of contamination. In some

ing or sources of contamination. In some

cases, flux contamination can show up

af-ter cure in a series of small

ter cure in a series of small bubbles on thebubbles on the

side of the die opposite the dispense side.

Apparently, fluid flow carries the flux to

the far side of the die.

Material Bubble Voids

As mentioned earlier, most material

sup-pliers are very careful about packaging

pliers are very careful about packaging

underfill material with air bubbles.

Im-proper handling, repackaging, or

proper handling, repackaging, or

dispens-ing technology can induce these issues. If

ing technology can induce these issues. If

air bubbles in the material are suspected,

there is a straightforward way to inspect

for this. Dispense the material from the

syringe through a fine needle and draw

a fine line in a long pattern, then inspect

for gaps in the dispensed line. If bubbles

in the material have been confirmed,

con-tact your material supplier about proper

tact your material supplier about proper

handling and storage of the fluid.

If no bubbles are found, this test can b

If no bubbles are found, this test can bee

repeated with the valve, pump, or jet

at-tached to the syringe. If

tached to the syringe. If voids occur dur-voids occur

dur-ing this test, and no voids were present

ing this test, and no voids were present

when dispensing directly from the

sy-ringe, then the equipment induced the

ringe, then the equipment induced the

bubbles. In this case, contact your

equip-ment supplier about proper setup and

ment supplier about proper setup and

equipment use.

Conclusion

Underfill voids can be a vexing

produc-tion problem. Understanding the

tion problem. Understanding the

charac-teristics of various root causes, and how to

teristics of various root causes, and how to

test for them, can help engineers resolve

the issues.

the issues. APAP

References

1. Babiarz, Alec J.,

1. Babiarz, Alec J.,Paradigm Shift in Applying Un-Paradigm Shift in Applying

Un-derfill

derfill, Pan Pacific Microelectronics Symposium,, Pan Pacific Microelectronics Symposium,

SMTA, 2005.

ALAN LEWIS, director of application engineering,

may be contacted at Asymtek, 2762 Loker Ave.

West, Carlsbad, CA 92010; 760/930-3379; e-mail:

[email protected].

Figure 2.

Figure 2.Use of glass and two colors of un-Use of glass and two colors of

un-derfill can help visualize flow and formation of

derfill can help visualize flow and formation of

flow-pattern voids.

Figure 3.

Figure 3.Jet dispensing the underfill, rath-Jet dispensing the underfill,

rath-er than needle dispensing, can avoid some

er than needle dispensing, can avoid some

causes of voiding under the die.

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0509AP_16 16

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8/26/05 12:29:55 8/26/05 12:29:55 PMPM

Advanced Advanced

Packaging

        F F F F

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Advanced Advanced

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IEEE 1451.4

FACILITATING TEMPERATURE SENSOR SUCCESS

BY CHRIS SEYMOUR

T

emperature sensors are usually consigned to supporting roles in semiconductor manufacturing and packaging. But, as in mov-ies, how supporting roles perform can be the difference between success and fail-ure. When problems with temperature accuracy, repeatability, or stability arise, the spotlight turns and remains fixed on temperature components.

In recent years, continuous and rapid advancements in the semiconductor in-dustry have thrust temperature sensors into the spotlight. Traditional sensors have struggled to keep pace, and often have been the weakest link in new or advanced processes. For example, many of

today’s applications, such as wafer and integrated circuit (IC) test and bonding applications, require an extremely tight temperature tolerance, and therefore, an extremely accurate sensor. During the past decade, the only way to make a sensor more accurate was to rely on tighter material property controls. Over the years, this has resulted in the use of purer and more homogenous elemental metals, which are often more costly and less readily available. This approach has only taken the industry so far. Process drift, unachievable levels of accuracy, and increasing costs drove the need to abandon this approach and search for more effective ways to improve sen-sor accuracy.

Two recent developments have emerged and converged to overcome the limitations of traditional sensors, and perhaps more importantly, to bring additional options and benefits to

pro-cesses. These developments include the use of smart-sensing technology and the development of the IEEE 1451.4 smart-sensing technology architecture standards. Today, many engineers in- volved in thermal processes are familiar with both developments, but have only

caught a glimpse of their potential. Smart sensors achieve high-level accu-racy not through the use of purer mate-rials, but by putting their known

charac-teristics to work. Specifically, four error values, known from sensor calibration, are transferred into a compatible temper-ature controller during installation. The controller takes these four offset points, connects them with three straight-line segments, and then performs a high-or-der curve fit to correct known errors. This process improves the sensor’s accu-racy because it knows the error limita-tions at specific temperatures and replac-es previously assumed tolerance windows with exact information. The result is less process variation, better efficiency, and improved yield.

The other development, the IEEE 1451.4 standards, is also capturing the attention of the industry. The standards define the parameters for plug-and-play analog sensors, their interface to exist-ing instrumentation, and the use of embedded transducer electronic data sheets (TEDS) to convey a sensor’s er-ror values automatically.

IEEE 1451.4 standards contribute to smart sensing as Ford’s assembly line eased automotive production. The stan-dards not only provide a universal for-mat for smart-sensing inforfor-mation and the hardware it uses, they also propel the quick adoption of smart sensing by elim-inating adaptability concerns — making the technology mainstream.

Still, users and potential users of smart sensors see only half of the technology’s potential. IEEE 1451.4-compliant in-strumentation offers previously unob-tainable levels of accuracy. But because the sensors no longer rely on the purity or composition of materials to achieve

Figure 1. The plug-and-play technology provides linking of the application to the calibration lab. S T A N D A R D S

2005 Sep AdvancedPkg

Underfill Voids

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Eliminating

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MEMS Update

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Sensors

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Recognition

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