ISSN 1450-216X / 1450-202X Vol. 150 No 2 September, 2018, pp. 126-151 http://www. europeanjournalofscientificresearch.com
Towards the Designing of Efficient Computing Reversible Fault Tolerant Arithmetic Circuits and ALU Biswajit Das
NIT Durgapur
PhD Scholar, NIT Durgapur, India
Saravanan Chandran
Associate Prof. Dept. of CSE, NIT Durgapur, India
Abstract
Fault tolerance property of reversible circuits is very important factor for designing fault free systems in the field of nanotechnology. It contributes an expansive category of finding faults in the circuit which can be detecting at the circuit outputs. Thus in a word reversible logic circuits having fault tolerance will be more beneficial. In this paper two new fault tolerant reversible gates RFTAAS and PPNG have been proposed for optimizing the circuit in terms of the gate number, garbage outputs, hardware complexity and constant inputs. This work targets realization of reversible Fault Tolerant Arithmetic circuits by the proposed gates. Two lemmas are also shown for the validation of being fault tolerant of these proposed gates. Moreover synthesis of full adder and fault tolerant full adder is done.
This paper presents the design of fault tolerant reversible arithmetic circuits and ALU units explored for trade-off between gate count, garbage outputs, anciallry input and quantum cost. The proposed work focuses on the design of dedicated arithmetic circuits and ALU units with generalized methodology for n-bit arithmetic circuits and ALU unit. The obtained results are compared with the existing state-of-art designs for performance and the design is found to be efficient in terms of the performance metrics.
Keywords: Reversible Logic, Quantum Cost, Garbage Output, Fault Tolerance, Parity- Preserving Reversible Gate, Adder, Arithmetic Logic Unit
1. Introduction
Reversible logic is the idea regarding the design of energy efficient system. It is very promising and important area to explore. Reversible logic has applications in more than a few fields such as low power CMOS design, optical information processing and quantum computing. The outlook of the reversible logic is to make digital devices without having power dissipation. As per Landauer [1], in the computations of irreversible circuit, for each bit an amount of energy 2 Joules is lost as a heat. This is the smallest amount of energy necessary for the processing of a bit. Bennett [2] showed that power dissipation of a logical circuit may be zero is achievable if it uses only reversible logic gates. A number of reversible gates have been anticipated in the literature survey such as Feynman [3], Toffoli, and Fredkin [4, 5] gates. On the other hand, parity preserving reversible circuits is the upcoming designing prospect for the growth of fault tolerant reversible systems. In several field of applications, fault tolerance is obtained by means of parity. This paper proposes two new parity preserving reversible gates RFTAAS (Reversible Fault Tolerant Arithmetic Adder Subtractor) and PPNG (Parity Preserving New Gate). Two lemmas are given here as a proof of the property of parity- preserving of the two proposed gates. This work also presents efficient reversible fault tolerant adder
circuits by our proposed gate. This work is structured such as Section 2, specifies the preliminaries about the reversibility and fault tolerance. Section 3 shows our proposed fault tolerant reversible gates and the proof of their parity preserving property. Section 4 shows synthesis of Reversible Full adder.
Section 5 describes the designing of different proposed Reversible Fault Tolerant adders. Section 6 describes the design of proposed Fault Tolerant ALU (Arithmetic Logic Unit). Section 7 shows the comparison outcome of the proposed circuits. Lastly, the conclusion is set in Section 8.
2. Preliminaries 2.1 Reversible Logic
A logic gate can be defined as reversible when the mapping of its input vectors to output vectors follow bijectivity for each specific output is related to the specific input and also the inputs are the same as to the outputs [7]. The main parameters in reversible logic circuit are the gate count, quantum cost, garbage output, hardware complexity and constant input.
2.2 Performance Metrics
The performance metrics considered in this paper for the assessment of reversible circuits are listed below.
Quantum Cost: The total number of quantum gates required in the design of a reversible gate is known as its Quantum Cost (QC). The quantum cost of each 2 × 2 gate is one and the cost of 1 × 1 gate is zero [8]. Every reversible logic circuit can be possible to implement with primitive gates such as 2 × 2 reversible gates and 1 × 1 NOT gates.
Garbage Outputs: The outputs that are added only to achieve reversibility which are called Garbage Outputs (GO). The inputs regenerated at the outputs are not garbage outputs as these outputs help for self-test purpose [1].
Ancillary Inputs: In reversible logic, those inputs which are kept constant to synthesize the required logical function using reversible gates are known as Ancillary Inputs (AI).
Gate Count: Gate Count (GC) is the number of reversible gates used to realize a reversible logic circuit.
Total Logical Calculation: Total Logical Calculation (TLC) is expressed by (Aα + Bß + Cδ).
Where α, ß and δ refers EX-OR operations, AND operations and NOT operations respectively and A, B and C specifies number of EX-OR operations, AND operations and NOT operations respectively.
Delay: The delay of a logic circuit is related to the maximum number of logic gates in a route from any input line to any output line. This definition is based on the following two assumptions [29], first one is related to the unit time computation of each gate. Second factors are the known inputs which are given to the circuit. Delay is calculated as the sum of delays of each gate. Interconnect delay is also a vital parameter as the semiconductor technology is marching towards lower sized chips [27, 28].The interconnect delay (tid) can be calculated as
tid= (3.56 *Κ L2 ρε )/(λ2 n)
Where, K = dielectric constant of metal, L = maximum interconnect wire length, ρ = wire resistivity,
ε = permittivity,
λ= least thickness value,
n= no. of lines broke for calculation for long lines.
Area: The area of a logic circuit is the summing up all the individual area of each gate of the circuit. If a reversible circuit consists of k reversible gates and area of those k gates are a1, a2, …, ak
then, area (A) can be given as
Power: The power of a logic circuit is the addition of all the individual power of each gate of the circuit.
If a reversible circuit consists of k reversible gates and individual power of those gates are p1, p2, …, pk, respectively. Then, the power (P) of the circuit is
2.1 Fault-Tolerant Logic
Fault tolerant system is capable to work correctly even in the occasion some of its elements fails. A fault tolerant reversible gate also can be said a conservative gate [9]. The parity of input vectors and output vectors must be equal. Let us consider the input vectors be IV= I0, I1. . . I −1 and OV = O0, O1. . . O −1, are the output vectors of any fault tolerant gate, where
(i) IV ⟨Bijective⟩ OV,
(ii) I1 ⊕ I2 ⊕…⊕ In-1↔O1 ⊕ O2 ⊕….⊕ On-1.
2.2 Fault Tolerant Reversible Logic Gate
Many fault tolerant reversible gates have been already anticipated by many authors. A small number of favorable parity preserving gates are given as follows:
Feynman Double Gate (F2G): It is a 3x3 Gate [10] having quantum cost two. The input vectors are specified as A, B and C and P = A, Q = A⊕ B, and R = A⊕C are the output vectors.
Fredkin Gate (FRG): A 3x3 Fredkin gate [11] has quantum cost is equal to five. The input vectors are specified as A, B and C and output vectors are given as P = A, Q= A’B ⊕AC and R = A’C
⊕AB.
Modified IG Gate (MIG): A 4x4 Modified IG gate [12] having four input vectors are specified as A, B ,C and D and four output vectors are given as P = A, Q = A ⊕B, R = AB ⊕C and S = AB’ ⊕D.
Islam Gate (IG): A 4x4 IG gate [13] is specified by the input vectors as A, B, C and D and output vectors are given as P = A, Q = A⊕ B, R = AB⊕C and S = BD⊕B’ (A⊕D).
New Fault Tolerant (NFT): A 3x3 NFT gate [14] is specified by the input vectors as A, B and C and output vectors are given as P = A⊕Β, Q = BC’⊕ AC’ and R = BC⊕ΑC’.
Toffoli Gate (TG): A 3x3 TG gate [15] is specified by the input vectors as A, B and C and output vectors are given as P = Α, Q = B and R = AB⊕C.
Fault Tolerant MUX (FTM): A 3x3 FTM gate [15] is specified by the input vectors as A, B and C and output vectors are given as P = Β, Q = B’A⊕ BC and R = B’C⊕ΒΑ.
3. Proposed Gates
In this section, we have proposed two new fault tolerant reversible gates named RFTAAS and PPNG in subsections 3.1 and 3.2 respectively. Truth table of these gates is also presented in this section which shows their reversibility as well as their parity preserving property. Two lemmas are also presented in this section to prove the parity preserving property.
k A =∑ ai
i=1
k P = ∑ pi
i=1
3.1 Proposed Fault Tolerant Reversible RFTAAS Gate
In this subsection, a new 5x5 fault tolerant reversible gate namely RFTAAS gate is proposed. The proposed gate and its truth table are given away in figure1 and table1 respectively. It can be notified from the truth table that the input bit pattern related to a specific output bit pattern can be possible to determine uniquely and find out the input-output bit parity. Therefore it can be said that the proposed RFTAAS gate is a reversible gate.
Figure 1: RFTAAS Gate
The quantum representation and transistor implementation of this proposed gate are shown in Figure 2 and Figure 3 respectively. The quantum cost of this proposed gate is 9. Total 92 MOS transistors are required to implement this proposed gate using CMOS technology.
Figure 2: Quantum Representation of RFTAAS Gate
Figure 3: Transistor Implementation of RFTAAS Gate
Table 1: Truth Table for RFTAAS Gate
Inputs Outputs
A B C D E P Q R S T
0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 1 0
0 0 0 1 0 0 1 1 1 0
0 0 0 1 1 0 1 1 0 0
0 0 1 0 0 0 1 0 0 0
0 0 1 0 1 0 1 0 1 0
0 0 1 1 0 0 0 1 1 0
0 0 1 1 1 0 0 1 0 0
Inputs Outputs
A B C D E P Q R S T
0 1 0 0 0 0 1 0 1 1
0 1 0 0 1 0 1 0 0 1
0 1 0 1 0 0 0 0 1 1
0 1 0 1 1 0 0 0 0 1
0 1 1 0 0 0 0 1 0 1
0 1 1 0 1 0 0 1 1 1
0 1 1 1 0 0 1 1 0 1
0 1 1 1 1 0 1 1 1 1
1 0 0 0 0 1 1 0 1 0
1 0 0 0 1 1 1 0 0 0
1 0 0 1 0 1 0 0 1 0
1 0 0 1 1 1 0 0 0 0
1 0 1 0 0 1 0 1 0 0
1 0 1 0 1 1 0 1 1 0
1 0 1 1 0 1 1 1 0 0
1 0 1 1 1 1 1 1 1 0
1 1 0 0 0 1 0 1 1 1
1 1 0 0 1 1 0 1 0 1
1 1 0 1 0 1 1 0 0 1
1 1 0 1 1 1 1 0 1 1
1 1 1 0 0 1 1 1 1 1
1 1 1 0 1 1 1 1 0 1
1 1 1 1 0 1 0 0 0 1
1 1 1 1 1 1 0 0 1 1
Lemma 1: Proposed RFTAAS Gate is a Fault Tolerant Gate
Proof: The input vectors and output vectors of RFTAAS gate are Iv = {A, B, C, D, E} and Ov
= [A, (A⊕B⊕C⊕D), {(A⊕B) (C⊕D) ⊕(ΑΒ ⊕D)},{(A⊕B)(C’⊕D) ⊕(ΑΒ ⊕D)⊕Ε},B] respectively.
From Section IIC, we can know that input parity and output parity will be same in fault tolerant or parity preserving gate.
Therefore, the input parity of RFTAAS gate is = [A⊕B⊕C⊕D⊕Ε ]
Output parity of FTM gate is = [A⊕ (A⊕B⊕C⊕D) ⊕ {(A⊕B) (C⊕D) ⊕ (ΑΒ ⊕D)}⊕ {(A⊕B)(C’⊕D)
⊕(ΑΒ ⊕D)⊕Ε} ⊕B]
= [A⊕A⊕B⊕C⊕D ⊕ (A⊕B)(C⊕D) ⊕(ΑΒ ⊕D)⊕(A⊕B)(C’⊕ D)⊕(ΑΒ ⊕D)⊕Ε⊕B]
= [0⊕B⊕C⊕D⊕ (A⊕B){(C⊕D) ⊕(C’⊕D)}⊕ (ΑΒ ⊕D) ⊕ (Α Β ⊕D) ⊕Ε ⊕B]
= [B⊕C⊕D⊕ (A⊕B){1}⊕ 0 ⊕Ε ⊕B ]
= [B⊕C⊕D⊕A⊕B⊕Ε ⊕B]
= [(B⊕ B) ⊕C⊕D⊕A⊕B⊕Ε]
= [0⊕C⊕D⊕A⊕B⊕Ε]
= [C⊕D⊕A⊕B⊕Ε]
= [A⊕B⊕ C⊕D⊕Ε]
Thus, output parity is equal to input parity. As RFTAAS gate preserves the parity values of input and output, it is a fault tolerant reversible gate.
3.2 Proposed Fault Tolerant Reversible PPNG Gate
In this subsection, a new 5x5 fault tolerant reversible gate namely PPNG gate is proposed. The proposed gate and its truth table are shown in Figure 4 and Table 2 respectively. It can be revealed from the truth table that the input pattern related to a particular output pattern can be uniquely determined and find out the input-output bit parity. Therefore it can be said that the proposed PPNG gate is a reversible gate.
Figure 4: PPNG Gate
The quantum representation and transistor implementation of this proposed gate are shown in Figure 5 and Figure 6 respectively. The quantum cost of this proposed gate is 13. Total 94 MOS transistors are required to implement this proposed gate using CMOS technology.
Figure 5: Quantum Representation of PPNG Gate
Figure 6: Transistor Implementation of PPNG Gate
Table 2: Truth Table for PPNG Gate
Inputs Outputs
A B C D E P Q R S T
0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 0 1 1 1
0 0 0 1 1 0 0 1 1 0
0 0 1 0 0 0 0 1 0 0
0 0 1 0 1 0 0 1 0 1
0 0 1 1 0 0 0 0 1 1
0 0 1 1 1 0 0 0 1 0
0 1 0 0 0 0 1 1 1 0
0 1 0 0 1 0 1 1 1 1
0 1 0 1 0 0 1 1 0 0
0 1 0 1 1 0 1 1 0 1
0 1 1 0 0 0 1 0 0 1
0 1 1 0 1 0 1 0 0 0
Inputs Outputs
A B C D E P Q R S T
0 1 1 1 0 0 1 0 1 1
0 1 1 1 1 0 1 0 1 0
1 0 0 0 0 1 0 1 1 0
1 0 0 0 1 1 0 1 1 1
1 0 0 1 0 1 0 1 0 0
1 0 0 1 1 1 0 1 0 1
1 0 1 0 0 1 0 0 0 1
1 0 1 0 1 1 0 0 0 0
1 0 1 1 0 1 0 0 1 1
1 0 1 1 1 1 0 0 1 0
1 1 0 0 0 1 1 0 0 0
1 1 0 0 1 1 1 0 0 1
1 1 0 1 0 1 1 1 1 1
1 1 0 1 1 1 1 1 1 0
1 1 1 0 0 1 1 1 0 0
1 1 1 0 1 1 1 1 0 1
1 1 1 1 0 1 1 0 1 1
1 1 1 1 1 1 1 0 1 0
Lemma 2: Proposed PPNG Gate is a Fault Tolerant Gate
Proof: The input vectors and output vectors of PPNG gate be Iv={A,B,C,D,E} and Ov=[A,B,{(A⊕B)’(C⊕D)⊕C’(A⊕Β)},{(A⊕B)(C⊕D)’⊕D(A⊕Β)’},{(A⊕B)(C⊕D) ⊕(D⊕Ε)}]
respectively . From section 2.3, we can be familiar with that input parity and output parity must have to be same in fault tolerant or parity preserving gate.
Thus, the input parity of PPNG gate is = [A⊕B⊕C⊕D⊕Ε]
Output parity of PPNG gate is
= [A⊕B⊕ {(A⊕B)’(C⊕D) ⊕ C’(A⊕Β)}⊕ {(A⊕B)(C⊕D)’⊕ D (A⊕Β)’}⊕{(A⊕B)(C⊕D) ⊕ (D⊕Ε)}]
= [A⊕B⊕ (A⊕B)’(C⊕D) ⊕ C’(A⊕Β)⊕ (A⊕B)(C⊕D)’⊕ D (A⊕Β)’⊕(A⊕B)(C⊕D) ⊕ (D⊕Ε)]
=[(A⊕B)(1⊕C’) ⊕(A⊕B){(C⊕D)’ ⊕(C⊕D)} ⊕(A⊕B)’{(C⊕D) ⊕ D}⊕ (D⊕Ε)]
= [(A⊕B) C ⊕ (A⊕B).1⊕ (A⊕B)’C ⊕ (D⊕Ε)]
= [C {(A⊕B) ⊕ (A⊕B)’}⊕(A⊕B) ⊕ (D⊕Ε)]
= [C.1⊕ (A⊕B) ⊕ (D⊕Ε)]
= [A⊕B⊕C⊕D⊕Ε]
Thus, output parity is equal to input parity. As PPNG gate preserves the parity values of input and output, PPNG gate is a fault tolerant reversible gate.
4. Synthesis of Fault Tolerant Reversible Full Adder Circuit
This part first establishes the minimum number of garbage outputs and constant inputs required to design a fault tolerant reversible full adder circuit.
Theorem 1: A full adder circuit can be realized with at least two garbage outputs and only one constant input [16].
Proof: The full adder circuit has two outputs, one is SUM and other one is CARRY. The equations are
SUM= (A ⊕ B ⊕ C in) and C out= {(A⊕B) C in ⊕ AB}
The output SUM =1 and C out= 0, for the three distinct input combinations A=0, B=0, C in=1; A=0, B=1, C in=0; and A=1, B=0, C in=0
Therefore, to separate all repeated values of outputs SUM and C out, at least two garbage outputs, are needed which is as shown in table 3. Therefore the total numbers of outputs are 2+2=4.
But it is known that in a reversible logic circuit the number of inputs must be equal to the number of
outputs. So as there are three inputs in a full adder circuit A, B and C in. Another input needs to be constant input. There are six combinations of input and outputs are given to comply the theorem 1.
Table 3: Truth Table for synthesizing Full Adder
Combination Input Output
A B Cin C1 Sum carry G1 G2
1
1 0 0 0 1 0 0 1
0 1 0 0 1 0 1 0
0 0 1 0 1 0 1 1
2
1 0 0 0 1 0 0 0
0 1 0 0 1 0 1 0
0 0 1 0 1 0 1 1
3
1 0 0 0 1 0 0 1
0 1 0 0 1 0 1 0
0 0 1 0 1 0 0 0
4
1 0 0 1 1 0 0 1
0 1 0 1 1 0 1 0
0 0 1 1 1 0 1 1
5
1 0 0 1 1 0 0 0
0 1 0 1 1 0 1 0
0 0 1 1 1 0 1 1
6
1 0 0 1 1 0 0 1
0 1 0 1 1 0 1 0
0 0 1 1 1 0 0 0
Theorem 2: A fault tolerant reversible full adder circuit can be realized with at least three garbage outputs and two constant inputs.
Proof: The full adder circuit has two outputs, one is SUM and other one is CARRY. The equations are
SUM= (A ⊕ B ⊕ C in) and C out= {(A⊕B) C in ⊕ AB}
The output SUM =1 and C out=0, for the three distinct input combinations A=0, B=0, C in=1; A=0, B=1,Cin=0; and A=1, B=0, C in=0.
The parity of the input vector matches the parity of the corresponding output vector. To separate all repeated values of outputs SUM and C out as well as keeping their parity unchanged we need at least three garbage outputs, as shown in table 4. So the total numbers of outputs are 2+3=5. But it is known that in a reversible circuit the number of inputs must be equal to the number of outputs. So as there are three inputs in a full adder circuit A, B and C in. Another two inputs need to be constant input. There are four combinations of input and output is given to comply the theorem 2.
Table 4: Truth Table for synthesizing FT-Full Adder
Combination Input Output
A B Cin C1 C2 S C G1 G2 G3
1
1 0 0 0 0 1 0 0 0 0
0 1 0 0 0 1 0 1 0 1
0 0 1 0 0 1 0 1 1 0
2
1 0 0 0 1 1 0 0 0 1
0 1 0 0 1 1 0 1 0 0
0 0 1 0 1 1 0 1 1 1
Combination Input Output
A B Cin C1 C2 S C G1 G2 G3
3
1 0 0 1 0 1 0 0 0 1
0 1 0 1 0 1 0 1 0 0
0 0 1 1 0 1 0 0 1 0
4
1 0 0 1 1 1 0 0 1 1
0 1 0 1 1 1 0 1 0 1
0 0 1 1 1 1 0 1 1 0
5. Proposed Designs for FT-ADDER
There are many fault tolerant reversible full adder circuits in the literature. The fault tolerant full adder circuit in [9] uses four FRGs and the fault tolerant full adder circuit in [19] requires six parity preserving reversible gates (two FRGs and four F2Gs). The fault tolerant full adder circuit in [20] uses two IG gate. The fault tolerant full adder circuit in [21] uses two MIG gate and one FRG gate. The fault tolerant full adder circuit in [23] uses two F2G gate and one FRG gate. This paper presents a new design of fault tolerant reversible full adder circuit that uses only one RFTAAS gate.
5.1 Proposed Fault Tolerant Reversible Full Adder-Subtractor
In this subsection, a new fault tolerant Adder-Subtractor is proposed. Only one RFTAAS gate is required for the designing that shown in Figure 7. For the realization of fault tolerant Adder-Subtractor two constant inputs are required. The circuit produces two garbage outputs and having hardware complexity of (8α+3ß+δ) and quantum cost nine. For CMOS transistor implementation total 92 MOS transistors are required .The functionality of this proposed circuit has been checked by the simulation using Xilinx 14.2.
Figure 7: Designing of Full Adder –Subtractor
Algorithm 1: Adder-Subtractor by RFTAAS gate:
1. Begin
2. Read: A, B, C, D, E 3. Set D=E=0
4. If (A==0,B==0, C==0)
5. then {P=garbage, Q=0,R=0,S=0,T=garbage}
6. Else
7. if (A==0,B==0, C==1)
8. then {P=garbage, Q=1,R=0,S=1,T=garbage}
9. If (A==0,B==1, C==0)
10. Then {P=garbage, Q=1,R=0,S=1,T=garbage}
11. Else
12. if (A==0,B==1, C==1)
13. then {P=garbage, Q=0,R=1,S=1,T=garbage}
14. end if
15. end if
16. If (A==1,B==0, C==0)
17. Then {P=garbage, Q=1,R=0,S=0,T=garbage}
18. Else
19. if (A==0,B==0, C==1)
20. then {P=garbage, Q=0,R=1,S=0,T=garbage}
21. If (A==1,B==1, C==0)
22. Then {P=garbage, Q=0,R=1,S=0,T=garbage}
23. Else
24. if (A==1,B==1, C==1)
25. then {P=garbage, Q=1,R=1,S=1,T=garbage}
26. end if 27. end if 28. End
5.2 Proposed Fault Tolerant 4 bit Reversible Ripple Carry Adder (FTRCA)
In this subsection 4 bit FTRCA has been designed by the proposed fault tolerant reversible RFTAAS gate. The circuit can add two four bit numbers (A3A2A1A0) and (B3B2B1B0) producing sum as S3S2S1S0 and final carry Cout. The design of FTRCA is shown in Figure 8. From figure we can see for the realization of 4 bit FTRCA only four RFTAAS gates and five constant inputs are required. The circuit produces nine garbage outputs and having total logical calculation of [4(8α+3ß+δ)]. Also 368 MOS transistors are needed to implement the circuit. For n-bit FTRCA designing n number of RFTAAS gates and (n+1) constant inputs are required. The n-bit circuit will produce (2n+1) garbage outputs and the Total Logical Calculation will be {n (8α+3ß+δ)}. Therefore the performance metrics for n bit ripple carry adder can be given as
GC=n GO=2n+1 QC=9n
TLC= {n (8α+3ß+δ)}
AI= (n+1)
Figure 8: Designing of 4 bit Ripple Carry Adder
The functionality of this proposed FTRCA circuit has been checked by the simulation using Xilinx 14.2. We have got the circuit delay and number of Slice LUT from the synthesis report.
Table 5: Performance Metrics for Ripple Carry Adder
Bits No. of Transistors Power(µw) Layout Area (µm2) Delay(ns) No. Slice LUT
n 92n 19.065x n n(438x20) 0.898n 3n
5.3 Proposed 4-bit Fault Tolerant Reversible Carry Look Ahead Adder (FTCLAA)
In this subsection 4 bit FTCLAA has been designed by the proposed fault tolerant reversible RFTAAS gate and existing fault tolerant reversible gate. The design of FTCLAA is shown in figure 9. From figure we can see for the realization of 4 bit FTCLAA, total thirteen gates are needed i.e only one F2G gate, four RFTAAS gates, four NFT gate, four TG gates are required. Also eleven constant inputs are required. The circuit produces fourteen garbage outputs and has total logical calculation of (50α+32ß+12δ). Also 646 MOS transistors are needed to implement the circuit. For n-bit (n=2m, m=1, 2, 3…) FTCLAA designing (3n+1) number of gates and (2n+3) constant inputs are required. The n-bit circuit will produce (3n+2) garbage outputs and the Total Logical Calculation will be {[(12n+2) α + (8n) ß+ (3n) δ].
Therefore performance metrics can be calculated as follows for n bit FTCLAA, GCn-bit =GC RFTAAS +GC NFT +GC TG+GCF2G
=(n+n+n+1)=(3n+1)
GO n-bit = GO RFTAAS +GO NFT +GO TG+GOF2G
=(1x1+nx1+nx2+1x1)
=(3n+2)
QC n-bit = QCRFTAAS +QC NFT +QC TG+QCF2G
=(nx9+nx7+nx5+1x2)
=(21n+2)
AI n-bit = [AIRFTAAS +AI NFT +AI TG+AIF2G]
={(n-1)x1+1x2}+(nx1)+nx0+1x2
=(2n+3)
TLC n-bit = TLCRFTAAS +TLC NFT +TLC TG+TLCF2G
= {n (8α+3ß+δ)} + {n (3α+4ß+2δ)} + {n (α + ß)} +2α
= [(12n+2) α + (8n) ß+ (3n) δ]
(Power )n-bit = [PRFTAAS +P NFT +P TG+PF2G]
=[(nx19.065)+(nx85.247)+(nx6.878)+(1x11.431)]µw
=(111.19n+11.431) µw
(Area)n-bit = [ARFTAAS +A NFT +A TG+AF2G]
=[n(438x20)+n(131x16)+n(49x13)+1x(49x13)]µm2
=(11493n+637) µm2
(No. of transistors) n-bit = [NTRFTAAS +NT NFT +NT TG+NTF2G]
=(nx92+nx48+nx16+1x22)
=(156n+22)
Table 6: Performance Metrics Carry Look Ahead Adder
Bits No. of Transistors Power(µw) Layout Area (µm2)
n 156n+22 (111.19n+11.431) (11493n+637)
Figure 9: Designing of 4 bit Carry look ahead adder
5.4 Proposed 4 bit Fault Tolerant Reversible Carry Skip Adder(FTRCSA)
In this subsection 4 bit FTRCSA has been designed by the proposed fault tolerant reversible RFTAAS gate and existing fault tolerant reversible gate. The design of FTRCSA is shown in Figure 10. From figure we can see for the realization of 4 bit FTRCSA total nine gates are needed i.e only one F2G gate,four RFTAAS gates, two PPNG gate, one TG gate and one FTM gate are required. Also eight constant inputs are required. The circuit produces forteen garbage outputs and has hardware complexity will be (51α+27ß+11δ). Also 640 MOS transistors are needed to implement the circuit .For n-bit (n=2m, m=1,2,3,….) FTRCSA designing (7n+8)/4 number of gates and (5n+12)/4 constant inputs are required. The n-bit circuit will produce (5n+8)/2 garbage outputs and Total Logical Calculation will be [ (47n/4) +4}α+{(23n/4) +4}ß+{(5n/2) +1}δ].
Therefore performance metrics can be calculated as follows for n bit FTRCSA, GCn-bit =GC RFTAAS +GC PPNG +GC TG+GCF2G+GCFTM
=(n+n/2+n/4+1+1)
=(7n+8)/4
GO n-bit = GO RFTAAS +GO PPNG +GO TG+GOF2G+GOFTM
={(n-1)x0+(1x1)}+{(n/2)x4}+{(n/4)x2}+1x1+1x2}
=(5n+8)/2
QC n-bit = QCRFTAAS +QC PPNG +QC TG+QCF2G+QCFTM
=[nx9+(n/2)x14+(n/4)x5+1x2+1x7]
=[9n+7n+(5n/4)+9]
=[16n+5n/4+9]
=[69n+36]/4
AI n-bit = AIRFTAAS +AI PPNG +AI TG+AIF2G+AIFTM
={(n-1)x1+1x2}+(n/2x0)+(n/4)x1+1x2+1x0
=[(5n+12)/4]
TLC n-bit = TLCRFTAAS +TLC PPNG +TLC TG+TLCF2G +TLCFTM
=[{n(8α+3ß+δ)}+{(n/2)x(7α+5ß+3δ)}+{(n/4)x(α + ß)+(1x2α)+ {1x (2α+4ß+δ)}]
= [(47n/4) +4}α+{(23n/4) +4}ß+{(5n/2) +1}δ].
(Power )n-bit = PRFTAAS +P PPNG +P TG+PF2G+PFTM
=[(nx19.065)+(n/2)x85.537+(n/4)x6.878)+(1x11.431)+ (1x33.397)]µw
=(63.553n +44.28) µw
(Area)N-BIT = ARFTAAS +A PPNG +A TG+AF2G+AFTM
=[n(438x20)+(n/2)(386x20)+(n/4)(49x13)+1x(49x13)1x(127x16)]µm2
=(12779.25n+2669) µm2
(No. of transistors) n-bit = NTRFTAAS +NT PPNG +NT TG +NTF2G +NTFTM
=(nx92+(n/2)x94+(n/4)x16+1x22+1x46)
=(143n+68)
The functionality of this proposed FTRCSA circuit has been checked by the simulation using Xilinx 14.2. We got the circuit delay and number of Slice LUT from the synthesis report.
Table 7: Performance Metrics of Reversible Carry Skip Adder
Bits No. of Transistors Power (µw) Layout Area(µm2) Delay (ns) No. Slice LUT
n (143n+68) (63.553n +44.28) (12779.25n+2669) 1.918 8
Figure 10: Designing of 4 bit Carry skip adder
5.5 Proposed 4 bit Fault Tolerant Reversible BCD Adder (FTBCDA)
In this subsection 4 bit FTBCDA has been designed by the proposed fault tolerant reversible RFTAAS and PPNG gate. The design of FTBCDA is shown in Figure 11. From figure we can see for the realization of 4 bit FTBCDA total eight gates are needed i.e,seven RFTAAS gates and one PPNG gate are required. Also ten constant inputs are required. The circuit produces tweenty garbage outputs has hardware complexity will be (63α+26ß+10δ). Also 738 MOS transistors are needed to implement the circuit .For n-bit (n=2m, m=2,3,….) FTBCDA designing [(9n/4)-1] number of gates and [(9n/4+1)]constant inputs are required. The n-bit circuit will produce 5n garbage outputs and Total Logical Calculation will be [{(71n/4)-8}α+{(29n/4)-3} ß+{(11n/4)-1}δ]. Therefore performance metrics can be calculated as follows for n bit FTBCDA,
GCn-bit =GC RFTAAS +GC PPNG
=[(2n-1)+n/4] =[(9n/4)-1]
GO n-bit = GO RFTAAS +GO PPNG
=[{(2n-3)x2+2x3}+{(n/4)x(1x4)}]
=(5n)
QC n-bit = QCRFTAAS +QC PPNG
=[(2n-1)x9+(n/4)x14]
=[43n/2-9]
AI n-bit = AIRFTAAS +AI PPNG
=[{(2n-3)x1+2x2}+(n/4)(1x1)}]
=[(9n/4+1)]
TLC n-bit = TLCRFTAAS +TLC PPNG
= [{(2n-1) x (8α+3ß+δ)} + {(n/4) x (7α+5ß+3δ)}]
= [{(71n/4)-8} α + {(29n/4)-3} ß+ {(11n/4)-1} δ]
(Power )n-bit = PRFTAAS + P PPNG
=[(nx19.065)+(n/4)x85.537)]µw
=(40.449n) µw
(Area)N-BIT = ARFTAAS +A PPNG
=[n(438x20)+(n/4)(386x20)] µm2
=(10690n) µm2
(No. of transistors) n-bit = NTRFTAAS +NT PPNG
=(2n-1)x92+(n/4)x94
=(415n/2-92)
Figure 11: Designing of 4 bit BCD adder
The functionality of this proposed FTBCDA circuit has been checked by the simulation using Xilinx 14.2. We got the circuit delay and number of Slice LUT from the synthesis report.
Table 8: Performance Metrics of Reversible BCD Adder
Bits No. of Transistors Power (µw) Layout Area (µm2) Delay(ns) No. Slice LUT
n (415n/2-92) 40.449n 10690n 2.751 10
6. Proposed Design for FTALU
This section describes the design of proposed reversible Fault Tolerant Arithmetic Logic Unit (FTALU) in two ways. The subsection 6.1 describes realization of FTALU-8 for 8 Arithmetic operations and the subsection 6.2 describes realization of FTALU-12 for 12 Arithmetic operations. The programmable characteristic is the major benefit of the proposed ALU. By programming the different selection values different ALU functions can be implemented. This programmable characteristic adds more flexibility in reversible FTALU.
6.1 Proposed 1 bit-FTALU-8 for 8 Arithmetic Operations
In this subsection 1 bit-FTALU-8 has been designed for 8 operations by the proposed fault tolerant reversible RFTAAS gate and existing fault tolerant reversible gate. The design of 1 bit-FTALU-8 is shown in Figure 12. From figure we can see for the realization of 1 bit-FTALU-8 needs two gates i.e.
one RFTAAS gate and one FTM gate are required. Also 2 constant inputs are required. The circuit produces five garbage outputs and has hardware complexity will be (10α+7ß+2δ). Figure 13 shows the
quantum representation of 1 bit-FTALU-8. Figure 14 shows the design of an n-bit FTALU-8 which is synthesized by cascading the 1-bit FTALU-8. For n-bit -FTALU-8 designing 2n number of gates and 2n constant inputs are required. The n-bit circuit will produce 5n garbage outputs and Total Logical Calculation (TLC) will be {n (10α+7ß+2δ)}. The different operations performed by the proposed FTALU-8 are shown in table 9.
Figure 12: Realization of 1 bit FTALU for 8 operations
Figure 13: Quantum Representation of 1 bit FTALU for 8 operations
Table 9: Table for 8 operations of FTALU-8
S1 S0 Cin Output(F) Function
0 0 0 A Transfer A
0 0 1 A+1 Increment A
0 1 0 A+B Add B to A
0 1 1 A+B+1 Add B to A plus 1
1 0 0 A+B’ Add 1’ complement of B to A
1 0 1 A+B’+1 Add 2’ complement of B to A
1 1 0 A-1 Decrement A
1 1 1 A Transfer A
Therefore performance metrics can be calculated as follows for n bit FTALU for 8 operations, GCn-bit =GC FTM +GC RFTAAS=[n+n]=2n
GO n-bit = GO FTM +GO RFTAAS
=[(nx2+nx3}] =(5n)
QC n-bit = QC FTM +QCRFTAAS =[(n)x7+nx9] =[16n]
TLC n-bit = TLC FTM +TLCRFTAAS
= [{n (2α+4ß+δ)} + {n x (8α+3ß+δ)}]
= [(10n) α+ (7n) ß+ (2n) δ]
AI n-bit = AI FTM +AI RFTAAS
=[{(nx0)+(nx2}]
=[(2n)]
(Power )n-bit = P FTM +P RFTAAS
=[(nx33.397)+ (nx19.065)]µw
=(52.462n) µw
(Area)N-BIT = A FTM +ARFTAAS
=[n(127x16)+ n(438x20)µm2 =(10792n)
(No. of transistors) n-bit = NTFTM +NT RFTAAS =(n)x46+(n)x92
=(138n)
The functionality of this proposed FTALU-8 circuit has been checked by the simulation using Xilinx 14.2. We got the circuit delay and number of slice LUT from the synthesis report.
Table 10: Performance Metrics of Reversible FTALU-8
Bits No. of Transistors Power (µw) Layout Area (µm2) Delay (ns) No. Slice LUT
n 138n 52.462n 10792n 1.065n 2n
Figure 14: Realization of n bit FTALU-8 for 8 operations
Algorithm 2: Arithmetic logic unit for 8 operations 1. Begin:
2. Read Ai, Bi, S1,S0,Cin , 3. if S1=0;
4. if S0=0;
if Cin=0, then F=A else F=(A+1);
5. if S0=1;
if Cin=0, then F=(A+B) else F=(A+B+1);
6. else 7. if S0=0;
if Cin=0, then F=(A+B’) else F=( A+B’+1);
8. if S0=1;
if Cin=0, then F=(A-1) else F=A;
9. End
6.1 Proposed FTALU-12 based on 12 Arithmetic and Logical Operations
In this subsection 1 bit-FTALU-12 has been designed for 12 operations by the proposed fault tolerant reversible RFTAAS gate and existing fault tolerant reversible gate. The design of 1 bit-FTALU-12 is shown in Figure 15. From figure we can see for the realization of 1 bit-FTALU-12 total five gates are needed i.e. one RFTAAS gate, one PPNG gate and three FTM gate are required. Also five constant inputs are required. The circuit produces nine garbage outputs and Total Logical Calculation will be (21α+20ß+7δ). Figure 16 shows the quantum representation of 1 bit-FTALU-8. Figure 17 shows the design of an n-bit FTALU-12 which is synthesized by cascading the 1-bit FTALU-12. For n-bit FTALU-12 designing 5n number of gates and 5n constant inputs are required. The n–bit circuit will produce 9n garbage outputs and Total Logical Calculation will be [(21n)α+(20n)ß+(7n)δ].The different operations performed by the proposed FTALU-12 are shown in Table 11.
Figure 15: Realization of 1 bit FTALU-12
Figure 16: Quantum Representation of 1 bit FTALU for 8 operations
The functionality of this proposed FTALU-12 circuit has been checked by the simulation using Xilinx 14.2. We have got the circuit delay and number of slice LUT from the synthesis report.
Table 11: Table for 12 Operations of FTALU-12
S2 S1 S0 Cin Output(F) Function
0 0 0 0 A Transfer A
0 0 0 1 A+1 Increment A
0 0 1 0 A+B Addition
0 0 1 1 A+B+1 Add with carry
0 1 0 0 A-B-1 Subtract with borrow
0 1 0 1 A-B Subtraction
0 1 1 0 A-1 Decrement A
0 1 1 1 A Transfer A
1 0 0 X A˅B OR
1 0 1 X AB XOR
1 0 0 X A˄B AND
1 0 1 X A’ Complement A
Therefore performance metrics can be calculated as follows for n bit FTALU for 12 operations, GCn-bit =GC FTM +GC RFTAAS+GC PPNG
=[3n+n+n]
=5n
GO n-bit = GO FTM +GO RFTAAS+GO PPNG
=[{(2nx1)+nx2}+nx3+nx2]
=(9n)
QC n-bit = QC FTM +QCRFTAAS+QCPPNG
=[(3n)x7+nx9+nx14]
=(44n)
TLC n-bit = TLC FTM +TLCRFTAAS+TLC PPNG
= [{3n (2α+4ß+δ)} + {n x (8α+3ß+δ)} + {n x (7α+5ß+3δ)}]
= [(21n) α + (20n) ß + (7n) δ]
AI n-bit= AI FTM +AI RFTAAS+AI PPNG
=[{(2nx1)+nx0}+nx1+nx2]
=(5n)
(Power )n-bit = P FTM +P RFTAAS +P PPNG =[(3nx33.397)+ (nx19.065)+(nx85.392)]µw =(204.648n) µw
(Area)N-BIT = A FTM +ARFTAAS+A PPNG
=[3n(127x16)+ n(438x20)+ n(386x20)]µm2
=(22576n) µm2
(No. of transistors) n-bit = NTFTM +NT RFTAAS +NT PPNG
=(3n)x46+(n)x92+(n)x94
=(324n)
The functionality of this proposed FTALU-12 circuit has been checked by the simulation using Xilinx 14.2. We got the circuit delay and number of slice LUT from the synthesis report.
Table 12: Performance Metrics Of Reversible FTALU-12
Bits No. of Transistors Power (µw) Layout Area (µm2) Delay (ns) No. Slice LUT
n 324n 204.648n 22576n 1.075n 2n
Figure 17: Realization of n bit FTALU
Algorithm 3: Arithmetic logic unit for 12 operations 1. Begin:
2. Read Ai, Bi, S2, S1,S0,Cin , 3. if S2=0;
4. if S1=0;
5. if S0=0;
if Cin=0, then F=A else F=(A+1);
6. if S0=1;
if Cin=0, then F=(A+B) else F=(A+B+1);
7. else 8. if S0=0;
9. if Cin=0, then F=(A-B-1) else F=(A-B);
10. if S0=1;
if Cin=0, then F=(A-1) else F=A;
11. if S2=1;
12. if S1=0;
13. if S0=0, then (F ˅A) else F=(A⊕B);
14. Else S1=1;
15. If S0=0, then (F ˄A) else F=A ‘
16. End
7. Results
This section is for the discussion of results and comparison of performance metrics for all the designs presented in this paper. Simulation results of the proposed gates are shown from figure 18 to figure 21.
Extensive comparison is made with existing Adders and existing ALU in this section. The figures calculated in this section are for higher order bits are considered. Additionally, the designs were functionally verified with VHDL using Xilinx ISE. Table 13 shows that proposed fault tolerant full adder is efficient with respect to the existing one in terms of number of gates, garbage output, ancillary input, quantum cost and Total Logical Calculation But though the fault tolerant full adder in [22]
contains only one gate, the proposed adder in [22] does not satisfy the parity preserving property if we see the truth table of the proposed adder in [22]. In [31] Reversible Fault Tolerant ALU of 12 operations is proposed which consists of seven gates one NFT gate, three Fredkin gate, two double Feynman gate and one HNG gate. But according to the Truth Table of HNG gate [32], it can be said that HNG gate is reversible but not a fault tolerant gate. It is known that a Fault Tolerant circuit must contain all the gates having fault tolerance property. Therefore the proposed ALU in [31] is not Fault Tolerant in nature. But Also Table 14 shows the comparison of proposed 4-bit fault tolerant carry skip adder and the existing one. Table 15 shows the comparison of proposed 4-bit fault tolerant BCD adder and the existing one. Table 16 shows the comparison of proposed 1-bit fault tolerant ALU and the existing one. Table 17 shows the comparison of proposed n-bit fault tolerant ALU and the existing one.
Finally the summary of performance metrics FTALU-8 and summary of performance metrics FTALU- 12 are given in table 18 and table 19 respectively.
The proposed fault tolerant ALU is much better in terms of performance metrics. As all the proposed circuits are verified by Xilinx 14.2, their simulation results are given from figure 22 to figure 27. Figure28 shows comparison Results of Proposed FTALU and existing one. Figure 29 shows comparison Results of Proposed FTALU-8 and FTALU-12.
Figure18: Simulation Results of RFTAAS gate using DSCH
Figure 19: Simulation Results of RFTAAS gate using Microwind
Figure 20: Simulation Results of PPNG gate using DSCH
Figure 21: Simulation Results of PPNG gate using Microwind
Table 13: Comparison of FT- FULLADDER
FT-Full Adder GC AI GO QC TLC
[24] 9 9 11 30 unknown
[25] 5 5 7 26 unknown
[21] 3 2 4 19 8α+8ß+3δ
[9] 5 2 4 25 8α+16ß+8δ
[19] 6 5 6 - 12α+8ß+2δ
[20] 2 2 3 - 8α+6ß+2δ
[23] 4 2 3 11 8α+4ß+δ
[14] 6 5 6 18 12α+8ß+4δ
[12] 2 2 3 14 8α+6ß+2δ
[18] 4 2 3 11 9α+4ß+δ
[22] 1 2 3 8 13α+4ß+δ
Proposed 1 2 3 9 8α+3ß+δ
Table 14: Comparison of 4-bit FTCSA
FT CSA GC AI GO TLC
[24] 40 39 48 unknown
[25] 20 19 28 unknown
[26] 28 31 40 unknown
[22] 9 10 14 62α+32ß+8δ
Proposed 9 8 14 77α+27ß+11δ
Table 15: Comparison of 4-bit FTBCDA
FT BCDA GC AI GO TLC
[24] 43 43 55 unknown
[25] 29 34 41 unknown
[21] 23 25 32 unknown
Proposed 8 10 20 96α+26ß+10δ
Table 16: Comparison of 1-bit FTALU
FT ALU No. of operations GC AI GO QC TLC
[22] 6 7 4 5 26 25α+12ß+3δ
[30] 4 7 6 7 41 20α+26ß+12δ
[31] 12 7 6 12 30 -
Proposed FTALU-8 8 2 2 5 16 13α+7ß+2δ
Proposed FTALU-12 12 5 5 9 44 (21α+20ß+7δ )
Table 17: Comparison of n-bit FTALU
FT ALU No. of operations GC AI GO QC TLC
[22] 6 7n 4n 5n 26n n(25α+12ß+3δ)
[30] 4 7n 6n 7n 41n n(20α+26ß+12δ)
Proposed FTALU-8 8 2n 2n 5n 16n n(10α+7ß+2δ)
Proposed FTALU-12 12 5n 5n 9n 44n n(21α+20ß+7δ )
Figure 22: Simulation Results of RFTAAS Adder-Subtractor using Xilinx
Figure 23: Simulation Results of FTRCA using Xilinx
Figure 24: Simulation Results of FTRCSA using Xilinx
Figure 25: Simulation Results of FTBCDA using Xilinx
Figure 26: Simulation Results of FTALU-8 using Xilinx
Figure 27: Simulation Results of FTALU-12 using Xilinx
Figure 28: Comparison Results of Proposed FTALU and existing one
0 50
GC G0
AI
QC
Comparison of performance metrices of FTALU
PROPOSED FTALU8 PROPOSED FTALU 12 [22] [30] [31]
