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ENVIRONMENT FOR SIGNAL PROCESSING APPLICATIONS DEVELOPMENT AND PROTOTYPING Brigitte SAGET, MBDA

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(1)

E

NVIRONMENT FOR

S

IGNAL

P

ROCESSING

A

PPLICATIONS

D

EVELOPMENT AND PR

O

TOTYPI

N

G

(2)

ESPADON objectives

ESPADON objectives

*

Define an advanced development methodology and specify a

Design Environment to support this methodology

*

Select the commercial tools to be integrated in the ESPADON

Design Environment

*

Implement the ESPADON Design Environment with its selected

tools

*

Benchmark the ESPADON methodology and Design

Environment with Signal Processing Test Applications

*

Demonstrate the benefit in terms of development cost and

(3)

Military systems development context

Military systems development context

DEVELOPMENT OF NEW MILITARY SYSTEMS CHANGES IN ELECTRONIC INDUSTRY INCREASED COMPLEXITY SHRINKING BUDGETS INCREASED COMPETITION (USA, WORLDWIDE) 1 GFlops/s 10 GFlops/s A few modes Multimodes Extended Multimodes 2000 1990 1980 PROCESSING POWER YEARS FUNCTIONS 60 80 100 120 140 700 600 500 400 300 USA FRANCE UK 40 20 NETHERLANDS 1990 1995 0 10 20 100 50 Billions of ECUs Billions of FF 0

(4)

Technology insertion concept

Technology insertion concept

MOORE’S LAW :

Electronics Performance Improvement : 2 X every 2 years

Conventional

Development

Method :

Final product

Prototype

Retrofit

Performance

"log" scale

Final product

P: Expected level of performance of the final product

T end of development

Programme Start

Time

1

rst

Prototype

2

nd

Prototype

Iterative

Development

Method :

Retrofit

(5)

Technology insertion,

Manufacture,

Integration & Test

COTS

RE-USED HARDWARE RE-USED SOFTWARE

AUTO-GEN CODE

NEW SOFTWARE NEW HARDWARE

HARDWARE

HARD/SOFT

CODEVELOPMENT

HARDWARE/SOFTWARE

COSIMULATION

SOFTWARE

Models

VIRTUAL PROTOTYPE

Virtual Prototyping & Technology Insertion

Virtual Prototyping & Technology Insertion

PERFORMANCE/

BEHAVIOURAL

SIMULATION

Models

HARDWARE / SOFTWARE ARCHITECTURAL DESIGN

FUNCTIONAL

SIMULATION

Models

FUNCTIONAL DESIGN

FUNCTIONAL

REFERENCE MODEL

CODE

(6)

Plan SP Development

R

i

s

k

R

e

g

i

s

t

e

r

R

e

q

u

i

r

e

m

e

n

t

s

D

e

v

e

l

o

p

m

e

n

t

P

l

a

n

From System Development

Functional Design

Architectural Design

Specification

Implementation

To System Development

System Review

The ESPADON Methodology

The ESPADON Methodology

Requirements

Risk Register

Risk Analysis Definition Development Validation

Development Plan From Previous Process

To Next/Previous Process Review

• Risk driven development life cycle

• « Model Year » approach

• Reuse and capitalisation

• Support for:

- Trace-ability

(7)

Plan SP Development

R

i

s

k

R

e

g

i

s

t

e

r

R

e

q

u

i

r

e

m

e

n

t

s

D

e

v

e

l

o

p

m

e

n

t

P

l

a

n

From System Development

Functional Design

Architectural Design

Specification

Implementation

To System Development

System Review

The ESPADON Methodology

The ESPADON Methodology

Risk driven development life cycle

« Model Year » approach

• Reuse and capitalisation

Support for:

- Trace-ability

- Cost performance trade off

Requirements

Risk Register

Risk Analysis Definition Development Validation

Development Plan From Previous Process

To Next/Previous Process Review

Phase 1:

Analysis and Selection of the requirements allocated to SP Subsystem GO/NO GO Phase 2: Definition of SP Subsystem Phase 4: Validation of SP Subsystem Phase 3: Development of SP Subsystem Example of risk:

Real time performance

Example of risk: SP algorithms, ... SP Functional definition Computer architecture choice Simulation Example of risk: Computing power Functional modelling Example of risk: Software development SP production Refinement of architecture choice Mapping description Hardware/Software description Placement of functions Development of performance model Software/Hardware development (synthesis) Production Integration Choice validation Validation of performance model Validation of virtual prototype Validation of manufactured computer

INCREASING LEVEL OF REFINEMENT

(8)

Tool List

Tool List

Project Planning

:

ARTEMIS - KUB Sistem SDN. BHD.

Requirements Analysis:

RTM - Marconi Systems Technology Inc.

RDD100 - Ascent Logic (US)

DOORS - Quality Systems Software Ltd.

Cost Estimation:

PRICE - Lockheed (US)

KNOWLEDGE - Software Productivity Research

Performance Simulation:

BONES - Cadence Design Systems Inc (US)

SES/WORKBENCH - SES (US)

OPNET - MIL 3 (US)

COSMOS - Omniview (US)

MODLINE - Simulog (Fr)

High Level Simulation:

SPW - Cadence Design Systems (US)

RIPPEN - Orincon (US)

SYSTEMVIEW - Elanex Inc (US)

GEDAE - Lockheed Martin ATL (US)

PTOLEMY - UCB (US)

MATLAB - The Math Works Inc (US)

MATLAB/SIMULINK - The Math Works Inc (US)

COSSAP - Synopsys Inc (US)

HP ESOF - HP

High Level Simulation

(continued):

DSP STATION - Mentor (US)

DSP CANVAS - Angels Design System (US)

HYPERSIGNAL BLOCK DIAGRAM - Hyperception (US)

MUSTIG - Gresilog (Fr)

PEAKWARE - Matra Systemes et Information

Control Simulation/FSM:

STATEMATE- I-Logix Inc.

MATRIXX - Integrated Systems Inc.

SYNCCHART/ESTEREL - Simulog (Fr)

OBJECTGEODE - Verilog (Fr)

Co-design/co-simulation:

FELIX/VCC - Cadence Design Systems Inc (US)

EAGLEI - Synopsys (US)

Seamless - Mentor (US)

COWARE - CoWare N2C (US)

AREXSYS - Arexsys (Fr)

Configuration Management:

CLEARCASE - Rational (US)

RCS/CCS - Freeware

Miscellaneous:

02 - Ardent software (US)

OBJECTSTORE - Object Design (US)

VERSANT - Versant (US)

(9)

Tools Selected - Rapid Prototyping

Tools Selected - Rapid Prototyping

EDE

Framework

Configuration

Mgmnt

(

CVS,

Clearcase

)

Matlab

Simulink/RTW

Ptolemy

GEDAE

Range of Target H/W

Target- Porting Kit

VSIP

MPI-RT

Algorithm

Prototyping

Libraries

Standards

Functional Design

Architectural Design

Implementation

(Rapid Prototyping)

Requirements Analysis

(RDD100, DOORS)

COST ESTIMATION

(PRICE)

External

Tools

(10)

Tools Selected - Virtual Prototyping

Tools Selected - Virtual Prototyping

Partitioning/Mapping

Linking

IP authoring tool

eg Handel C/ ART

DSP

Libs

Opt.

Libs

FPGA

Range of Target H/W

Processors

Functional Design/Simulation

e.g. Ptolemy/GEDAE

Process

Current proposition

(11)

Software

Design

Hardware

Design

OS, drivers

& Legacy code

IP Libraries

System C,

VHDL, VERILOG

Planned Solution for Virtual Prototyping

Planned Solution for Virtual Prototyping

Co

Verification

«C»

HDL

Links to Implementation

Communication

Refinement

Functional Simulation

System

Behaviour

ESPADON Platform

Integration

Behavioural

Libraries

Architecture

Definition

Architecture

Characterisation

Data books, IP

Architecture

Libraries

Performance

Simulation

Mapping

(12)

Results

Results

*

Definition of a process and a methodology

addressing obsolescence and COTS insertion issues through rapid

and virtual prototyping, for Signal Processing applications

*

Overview of the required techniques and available

technologies and tools

*

Demonstration of resulting productivity gains through

representative radar & sonar benchmarks (adaptive

beamforming)

Demonstrated x1.4 to x 16 Productivity (V0)

(13)

ESPADON Demonstrated Benefits

ESPADON Demonstrated Benefits

*

Reduction of development cost and time

productivity improvement : code generation

reduction of errors : early validation by simulation

dealing with late changes: delaying the need for hardware prototypes

*

Reduction of programme risks

risk driven process

incremental approach : simulation and prototyping

*

Mitigation of obsolescence problems / Retrofit

technology insertion through rapid prototyping

process based on a functional model and code generation facilitate the porting of

an application on different architectures : PPC => FPGA

*

Facilitation of collaborative developments

complexity management

reuse libraries

References

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