Complete Vlsi Notes

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JAIN University – Regulations, Scheme & Syllabi B.E (Electronics & Communication Engineering). 2009-10

7

Semester –VI

Digital VLSI Design

Subject Code: EC 64 Total No. of Hrs: 48

Credits: 4 Hours per week: 4

MOS Transistor Theory

Introduction, MOS device design equations, Complementary CMOS Inverter-DC characteristics, Static Load MOS Inverters, Differential Inverter, Transmission Gate, Tristate Inverter, Bipolar devices

CMOS Processing Technology

Silicon semiconductor technology An overview, basic CMOS technology, CMOS process enhancements, Layout Design rules, Latchup, Technology related CAD issues

Circuit Characterization and performance Estimation

Resistance Estimation, Capacitance Estimation, Inductance, Switching Characteristics, CMOS gate transistor sizing, Power dissipation, sizing routing conductors, charge sharing, Design Margining, Yield, reliability

Scaling of MOS circuits

Scaling principles, Interconnect layer scaling, Scaling models and scaling factors, scaling factors for device parameters, some discussion on scaling, and limitations of scaling. CMOS Circuit and Logic Design

Introduction, CMOS Logic Gate Design, Basic Physical Design of Simple Logic Gates, CMOS Logic Structures Clocking Strategies, I/O Structures, Low power Design CMOS Subsystem Design I

Introduction, Data path operations- Addition/ subtraction, Parity Generators, Comparators, Zero/one detectors, Binary counters, Boolean operations-ALUs, Multiplication, Shifters

CMOS Subsystem Design II

Memory Elements, Control-FSM, Control Logic Implementation

Reference Books:

1. Principles of CMOS VLSI design – Neil Weste & Kamaran Eshraghian

2. CMOS Digital Integrated Circuits Analysis and Design- Sung-mo-kang & Yusuf Leblebici

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Digital VLSI Design, ECE Dept.SET,JU. Page 1

MOS Transistor Theory

Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Introduction

The Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is the fundamental building block of MOS and CMOS digital integrated circuits. Compared to the bipolar junction transistor (BJT), the MOS transistor occupies a relatively smaller silicon area, and its fabrication involves fewer processing steps. These technological advantages, together with the relative simplicity of MOSFET operation, have helped make the MOS transistor the most widely used switching device in VLSI and VLSI circuits.

The MOSFET is a four terminal device. The voltage applied to the gate terminal determines if and how much current flows between the source and the drain ports. The body represents the fourth terminal of the transistor. Its function is secondary as it only serves to modulate the device characteristics and parameters.

At the most superficial level, the transistor can be considered to be a switch. When a voltage is applied to the gate that is larger than a given value called the threshold voltage VTh, a conducting channel is formed between drain and source. In the presence of a voltage difference between the latter two, current flows between them. The conductivity of the channel is modulated by the gate voltage—the larger the voltage difference between gate and source, the smaller the resistance of the conducting channel and the larger the current.

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Digital VLSI Design, ECE Dept.SET,JU. Page 2 A conducting channel will eventually be formed through applied gate voltage in the section of the device between the drain and the source diffusion regions. The distance between the drain and source diffusion regions is the channel length L, and the lateral extent of the channel (perpendicular to the length dimension) is the channel width W. Both the charnel length and the channel width are important parameters which can be

used to control some of the electrical properties of the MOSFET.

The thickness of the oxide layer covering the channel region, tox, is also an important parameter.

ENHANCEMENT-mode and DEPLETION-mode MOSFET.



1. ENHANCEMENT-mode MOSFET:

 A MOS transistor which has no conducting channel region at zero gate bias is called 'an enhancement-type (or enhancement-mode) MOSFET.

 MOSFET diagram

 n-channel and p-channel enhancement MOSFET normally OFF, below Threshold and above VTh on

 + VGS in n-MOSFET and - VGS in p-MOSFET  Symbol:



2. DEPLETION-mode MOSFET :

 If a conducting channel already exists at zero gate bias, on the other hand, the device is called a depletion-type (or depletion-mode) MOSFET.

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Digital VLSI Design, ECE Dept.SET,JU. Page 3  MOSFET diagram

 n-channel and p-channel Depletion MOSFET normally ON, Pinch off on  –VGS in n-MOSFET and + VGS in p-MOSFET

 Symbol

MOSFET Explanation

 In a MOSFET with p-type substrate and with n+ source and drain regions, the channel region to be formed on the surface is n-type. Thus, such a device with p-type substrate is called an n-channel MOSFET. 



 In a MOSFET with n-type substrate and with p+ source and drain regions, on the other hand, the channel is p-type and the device is called a p-channel MOSFET.  

 The device terminals are: G for the gate, D for the drain, S for the source, and B for the substrate (or body). 



 In an n-channel MOSFET, the source is defined as the n region which has a lower potential than the other n region, the drain. 



 By convention, all terminal voltages of the device are defined with respect to the source potential. Thus, the gate-to-source voltage is denoted by VGS, the

drain-to-source voltage is denoted by VDS, and the substrate-to-source voltage is denoted 

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Digital VLSI Design, ECE Dept.SET,JU. Page 4 Consider first the n-channel enhancement-type MOSFET shown in Figure. The simple operation principle of this device is: control the current conduction between the source and the drain, using the electric field generated by the gate voltage as a control variable. Since the current flow in the channel is also controlled by the drain-, to-source voltage and by the substrate voltage, the current can be considered a function of these external terminal voltages. In order to start current flow between the source and the drain regions, however, we have to form a conducting channel first.

Region of Operation

I. Cut off Region

When gate-to-source voltage is less than threshold voltage i.e., VGS <VTh . There will be no channel across the surface and no current between source and drain i.e., ID=0 as show in above figure.

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II. Resistive/Linear Operation (Active Region)

Now assume that the gate-to-source voltage is further increased. The conducting n-type layer will form between the source and the drain diffusion regions as shown in below figure. This channel now provides an electrical connection between the two n+ regions, and it allows current flow, as long as there is a potential difference between the source and the drain terminal voltages. The bias conditions for the onset of surface inversion and for the creation of the conducting channel are therefore very significant for MOSFET operation.

Now VGS > VTh and that a small voltage, VDS, is applied between drain and source. The voltage difference causes a current ID to flow from drain to source. Using a simple analysis, a first-order expression of the current as a function of VGS and VDS can be obtained.

At a point x along the channel, the voltage is V(x), and the gate-to-channel voltage at that point equals VGS – V(x). Under the assumption that this voltage exceeds the threshold voltage all along the channel, the induced channel charge per unit area at point x can be computed.

Qi(x) = –Cox[VGS – V(x) – VTh]---1.1

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Digital VLSI Design, ECE Dept.SET,JU. Page 6 With ox = 3.97o = 3.5 10

-11

F/m the oxide permittivity, and tox is the thickness of the oxide.

The current is given as the product of the drift velocity of the carrier’s n and the

available charge. Due to charge conservation, it is a constant over the length of the channel. W is

the width of the channel in a direction perpendicular to the current flow. --- 1.2

The electron velocity is related to the electric field through a parameter called the mobility (expressed in m2/V s). The mobility is a complex function of crystal structure, and local electrical field. In general, an empirical value is used.

---1.3

---1.4 Substitute equations 1.1 and 1.3 in 1.2 yields

Integrating the equation over the length of the channel L yields the voltage-current relation of the transistor with boundary conditions x=0 to L and V=0 to VDS along the channel

---1.5 Where k_n’_, is called the process transconductance parameter and equals

---1.6

The W and L parameters in Equation the effective channel width and length of the transistor respectively.

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III.

The Saturation Region

As the value of the drain-source voltage is further increased, the assumption that the channel voltage is larger than the threshold all along the channel ceases to hold. This happens when VGS V(x) < VTh. At that point, the induced charge is zero, and the conducting channel disappears or is pinched off.

Figure shows that the current is not valid beyond the linear region/ saturation region boundary, i.e., for

V

DS DSAT

= V

GS

- V

Th---1.7

Also, drain current measurements with constant VS show that the current I_D does not show much variation as a function of the drain voltage. VDS beyond the saturation boundary, but rather remains approximately constant around the peak value reached for V_DS = V_{DSAT .}This saturation drain current level can be found simply by substituting Eq.5 in Eq.4

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Digital VLSI Design, ECE Dept.SET,JU. Page 9 MOSFET Current-Voltage Characteristics

Figure shows the typical drain current versus drain voltage characteristics of an n-channel MOSFET, as described by the current equations (4) and (6). The parabolic boundary between the linear and the saturation regions is indicated here. The current-voltage characteristics of the MOS transistor can also be visualized by plotting the drain current as a function of the gate voltage, as shown in Fig. This ID Versus VGS transfer characteristic in saturation mode (VDS > VDSAT) provides a simple view of the drain current increasing as a second-order function of the gate-to source voltage The current is obviously equal to zero for any gate voltage smaller than the threshold voltage VT

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Digital VLSI Design, ECE Dept.SET,JU. Page 10 Body effect on Threshold Voltage

As the gate voltage increases, the potential at the silicon surface at some point reaches a critical value, where the semiconductor surface inverts to n-type material. This point marks the onset of a phenomenon known as strong inversion and occurs at a voltage equal to twice the Fermi Potential.

---1.9

Further increases in the gate voltage produce no further changes in the depletion layer width, but result in additional electrons in the thin inversion layer directly under the oxide. These are drawn into the inversion layer from the heavily doped n+ source region. Hence, a continuous n-type channel is formed between the source and drain regions, the conductivity of which is modulated by the gate-source voltage. In the presence of an inversion layer, the charge stored in the depletion region is fixed and equals

---1.10

This picture changes somewhat in case a substrate bias voltage VSB is applied (VSB is normally positive for n-channel devices). This causes the surface potential required for strong inversion to increase and to become |–2 F + VSB|. The charge stored in the depletion region now is expressed by

---1.11

The value of the gate-to-source voltage VGS needed to cause strong surface inversion (to create the conducting channel) is called the threshold voltage VTh.

VTh is a function of several components, most of which are material constants such as the difference in work-function between gate and substrate material,

the oxide thickness, the Fermi voltage,

the charge of impurities trapped at the surface between channel and gate oxide, and The dosage of ions implanted for threshold adjustment.

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Digital VLSI Design, ECE Dept.SET,JU. Page 11 an impact on the threshold as well.

We rely on an empirical parameter called VT which is the threshold voltage for VSB = 0, and is mostly a function of the manufacturing process. The threshold voltage under different body-biasing conditions can then be determined in the following manner,

---1.12

The parameter (gamma) is called the body-effect coefficient, and expresses the impact of changes in VSB.

---1.13

Substrate Bias Effect

Note that the derivation of linear-mode and saturation-mode current-voltage characteristics in the previous pages has been done under the assumption that the substrate potential is equal to the source potential, i.e., VSB = 0. Consequently, the zero-substrate bias threshold voltage VTh has been used in the current equations. In many digital circuit applications, on the other hand, the source potential of an nMOS transistor can be larger than the substrate

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Digital VLSI Design, ECE Dept.SET,JU. Page 12 potential, which results in a positive source-to-substrate voltage VSB > 0. In this case, the influence of the nonzero VSB upon the current characteristics must be accounted for.

We can simply replace the threshold voltage terms in linear-mode and saturation-mode current equations with the more general VTh(VSB) term.

Channel Length Modulation

We will examine the mechanisms of channel pinch-off and current flow in saturation mode. Consider the inversion layer charge Qi that represents the total mobile electron charge on the surface. The inversion layer charge at the source end of the channel is

Q(X=0 ) = -COX (VGS-VTh) and the inversion layer charge at the drain end of the channel is

Q,(x= L) = -CoX (VGS - VTh - VDS))---1.14

Note that at the edge of saturation, i.e., when the drain-to-source voltage reaches VDSAT,

VDS = VDSAT = VGS - VTh

The inversion layer charge at the drain end becomes zero according to Eq. 1.14.In reality, the channel charge does not become exactly equal to zero but it indeed becomes very small.

CMOS (COMPLEMENTARY MOSFET)

MOS INVERTERS: STATIC CHARACTERISTICS

The logic symbol and the truth table of the ideal inverter are shown in Figure, In MOS inverter circuits, both the input variable A and the output variable B are represented by node voltages, referenced to the ground potential. Using positive logic convention, the Boolean (or logic) value of "1" can be represented by a high voltage of VDD, and the Boolean (or logic) value of "0" can be represented by a low voltage of 0. The DC voltage transfer characteristic (VTC) of the ideal inverter circuit is shown in Figure.

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Digital VLSI Design, ECE Dept.SET,JU. Page 13 The voltage Vth is called the inverter threshold voltage. Note that for any input voltage between 0 and Vth = VDD/2 , the output voltage is equal to VDD (logic" 1 ). The output switches from VDD to 0 when the input is equal to Vth. For any input voltage between Vth and VDD, the output voltage assumes a value of 0 (logic "0"). Thus, an input voltage 0 < Vin. < Vth is interpreted by this ideal inverter as a logic "0," while an input voltage Vth <Vin < VDD is interpreted as a logic “1." The VT characteristics of the ideal Inverter shown in below Figure. Noise Immunity and Noise Margins

To illustrate the effect of noise on the circuit reliability, we will consider the circuit consisting of three cascaded inverters, as shown in below Figure. Assume that all inverters are identical, and that the input voltage of the first inverter is equal to VOH, i.e., logic “1." By definition, the output voltage of the first inverter will be equal to VOL corresponding to a logic "0" level.

 VIL is the maximum allowable voltage at the input of the second inverter, which is low enough to ensure a logic "1" output

 VIH is the minimum allowable voltage at the input of the third inverter which is high enough to ensure a logic "0" output.

These observations lead us to the definition of noise tolerances for digital circuits, called noise margins and denoted by NM. The noise immunity of the circuit increases with NM. Two noise margins will be defined: the noise margin for low signal levels (NML) and the noise margin for high signal levels (NMH). For a gate to be robust and insensitive to noise disturbances, it is essential that the “0” and “1” intervals be as large as possible. A measure of the sensitivity of a gate to noise is given by the noise margins

LOW noise margin NML=VIL-VOL

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Digital VLSI Design, ECE Dept.SET,JU. Page 14 VOH: Maximum output voltage when the output level is logic “1”

VOL: Minimum output voltage when the output level is logic “0”

VIL: Maximum input voltage which can be interpreted as logic "0"

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CMOS inverter

Now, we will turn our attention to a radically inverter structure, which consists of an enhancement-type NMOS transistor and an enhancement-type PMOS transistor, operating in complementary mode. This configuration is called Complementary MOS (CMOS). The circuit topology is complementary push-pull in the sense that for high input, the NMOS transistor drives (pulls down) the output node while the PMOS transistor acts as the load, and for low input the PMOS transistor drives (pulls up) the output node while the NMOS transistor acts as the load. Consequently, both devices contribute equally to the circuit operation characteristics.

The CMOS inverter has two important advantages over the other inverter configurations.

 The first and perhaps the most important advantage is that the steady-state power dissipation of the CMOS inverter circuit is virtually negligible, except for small power dissipation due to leakage currents.

 The other advantages of the CMOS configuration are that the voltage transfer characteristic (VTC) exhibits a full output voltage swing between 0 V and VDD, and that the VTC transition is usually very sharp. Thus, the VTC of the CMOS inverter resembles that of an ideal inverter.

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Digital VLSI Design, ECE Dept.SET,JU. Page 16 VTC curve and output Voltage at different region of operation

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Digital VLSI Design, ECE Dept.SET,JU. Page 17 Region A:

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Digital VLSI Design, ECE Dept.SET,JU. Page 18 Region C:

PMOS, NMOS: saturation

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Digital VLSI Design, ECE Dept.SET,JU. Page 20 Region D:

Region E:

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Beta Ratio Effects

k

R

=

We have seen that for kp = kn, the inverter threshold voltage Vth is VDD/2. This may be desirable because it maximizes noise margins and allows a capacitive load to charge and discharge in equal times by providing equal current source and sink capabilities. Inverters with different beta ratios kR= kn /kp are called skewed inverters

 If kR < 1, the inverter is HI-skewed.  If kR >1, the inverter is LO-skewed.

 If kR = 1, the inverter has normal skew or is unskewed.

A HI-skew inverter has a stronger pMOS transistor. Therefore, if the input is VDD /2, we would expect the output will be greater than VDD /2. In other words, the input threshold must be higher than for an unskewed inverter. Similarly, a LO-skew inverter has a weaker pMOS transistor and thus a lower switching threshold.

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Static Load MOS Inverters

The figure shows a NMOS inverter with resistive load or a constant current source. For resistor load, if we superimpose the resistor load line on VI characteristics of Pull down transistor as in figure B, we can see that at VGS=5 volts, the output is some small VDS(VOL).when VGS=0volts,VDS rises to 5 volts.

 As resistor load is made larger, the VOL decreases and current flowing when inverter is turned on decreases.

 As resistor load is made smaller, the VOL increase and on current increases

 Selection of resistor value would seek compromise between VOL, the current drawn and the pull up speed

Note that the driver MOSFET is initially in saturation, since its drain-to source voltage.

(V

Ds

= V

0ut

=V

DD

) is larger than (V

in

- V

th

) =V

GS

-V

th

V

Ds

>> V

GS

-V

th

NMOS Saturation current is given by

I

R

=k

n

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Digital VLSI Design, ECE Dept.SET,JU. Page 23 With increasing input voltage, the drain current of the driver also increases, and the

output voltage Vout starts to drop.

 Eventually, for input voltages larger than Vout + Vth, the driver transistor enters the linear operation region. At larger input voltages, the transistor remains in linear mode, as the output voltage continues to decrease.

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The Pseudo nMOS Inverter

The Pseudo nMOS Inverter uses a p device pull up or load that has its gate is permanently grounded. An n-device pull down or driver is driven with the input signal. This is roughly equivalent to use of load in nMOS technology and is thus called “pseudo-nMOS”

When driver is turned on, constant DC current flows in the circuit. This is to contrasted with CMOS inverter in which no DC current flows when the input is either the terminal high or low state. The importance of whether DC current flows, and hence whether one can use pseudo nMOS inverter, depends on application

Derivation of output voltage equation and

n

/

p Consider PMOS

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Consider NMOS

PMOS always in ACTIVE region

for

V

_GS

<V

_Th,p

NMOS in Saturation region

for V

GS

>V

Th,n

and V

DS

> V

GS

-V

Th,n

V

out

> V

in

-V

thn

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Transmission gate

The strength of a signal is measured by how closely it approximates an ideal voltage source. In general, the stronger a signal, the more current it can source or sink. The power supplies, or rails, (VDD and GND) are the source of the strongest 1s and 0s

An nMOS transistor is an almost perfect switch when passing a 0 and thus we say it passes a strong 0. However, the nMOS transistor is imperfect at passing a 1. The high voltage level is somewhat less than VDD; NMOS transistors pass ‘0’s well but 1s poorly. We are now ready to better define “poorly.” Figure shows an nMOS transistor with the gate and drain tied to

VDD. Imagine that the source is initially at Vs = 0. Vgs > VTh, so the transistor is ON and current

flows. If the voltage on the source rises to Vs = VDD – Vth, Vgs falls to Vth and the transistor cuts itself OFF. Therefore, nMOS transistors attempting to pass a 1 never pull the source above

VDD – Vth

Similarly, pMOS transistors pass 1s well but 0s poorly. If the pMOS source drops below |Vtp|, the transistor cuts off. Hence, pMOS transistors only pull down to within a threshold above GND, as shown in Figure

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Digital VLSI Design, ECE Dept.SET,JU. Page 38 When an nMOS or pMOS is used alone as an imperfect switch, we sometimes call it as a pass

transistor. By combining an nMOS and a pMOS transistor in parallel. We obtain a switch that

turns on when a 1 is applied to g, in which 0s and 1s are both passed in an acceptable fashion. We term this a transmission gate or pass gate. In a circuit where only a 0 or a 1 has to be passed, the appropriate transistor (n or p) can be deleted, reverting to a single nMOS or pMOS device. Note that both the control input and its complement are required by the transmission gate. This is called double rail logic. Some circuit symbols for the transmission gate are shown in Figure.

Thus, the nMOS transistors only need to pass 0s and the pMOS only pass 1s, so the output is always strongly driven and the levels are never degraded. This is called a fully

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TRISTATE INVERTER

Figure shows symbols for a tristate Inverter. When the enable input EN is 1, the output

Y equals the input complement of A, just as in an ordinary inverter. When the enable is 0, Y is left

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Digital VLSI Design, ECE Dept.SET,JU. Page 41 Figure shows a tristate inverter. The output is actively driven from VDD or GND, so it is a restoring logic gate. The tristate inverter does not obey the conduction complements rule because it allows the output to float under certain input combinations.

When EN is 0, both enable transistors are OFF, leaving the output floating.

When EN is 1, both enable transistors are ON. They are conceptually removed from the circuit, leaving a simple inverter.

Tristate were once commonly used to allow multiple units to drive a common bus, as long as exactly one unit is enabled at a time. If multiple units drive the bus, contention occurs and power is wasted. If no units drive the bus, it can float to an invalid logic level that causes the receivers to waste power. Moreover, it can be difficult to switch enable signals at exactly the same time when they are distributed across a large chip. Delay between different enables switching can cause contention. Given these problems, multiplexers are now preferred over tristate busses.

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Differential Inverter

All of the that we hace examined so far is single ended;that is.they have single end input and produces single output. Now an inverter that uses two differential inputs and produces two differential outputs is as shown in figure,

Two n transistors have their sources commoned and fed by a constant current source that in turn connected to ground

The drains of each n transistor are connected to resistor load that are connected to the supply voltage.

Now we make some analysis, if the input voltage is applied ie., Vleft= VA= VRightthen each transistor has VGS=VA-VN, where VNis the voltage accrossthe constant current source. Thus is IDS is same for both the MOSFET and also Vout1=Vout2.

Now increase the Vleft and VRight equally,then VN also rises to maintain the constant current through the current source. The ouput voltages Vout1 and Vout2 will stay at same value.

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Digital VLSI Design, ECE Dept.SET,JU. Page 43 Applying common signal to both the inputs therefore results no gain(ideally). This gain is reffered as Common mode gain.

Now Vleft is increased by right is decreased by ,then current in N1 increases by and Vout1decreases by out2 increases by

Thus is the differential gain from V

left

to V

out

g

mis

/ V transconductance of the driver transistor

V

out1

=V

DD

- (I

source

*R

load

)/2

BIPOLAR DEVICES

1. DIODE 2. BJT 3. BiCMOS

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BiCMOS Inverter

BiCMOS Inverter

Two bipolar transistors (T3 and T4), one nMOS and one pMOS transistor (both enhancement- type devices)

 The MOS switches perform the logic function & bipolar transistors drive output loads

 Vin = 0 :

T1 is off. Therefore T3 is non-conducting T2 ON - supplies current to base of T4 T4 base voltage set to Vdd.

T4 conducts & acts as current source to charge load CL towards Vdd. Vout rises to VDD - VBE (of T4)

Note: V_BE (of T4) is base-emitter voltage of T4.

(Pull-up bipolar transistor turns off as the output approaches 5V - V_BE (of T4))  Vin = V

DD :

T2 is off. Therefore T4 is non-conducting. T1 is on and supplies current to the base of T3

T3 conducts & acts as a current sink to discharge load CL towards 0V. Vout falls to 0V+ VCEsat (of T3)

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Digital VLSI Design, ECE Dept.SET,JU. Page 2  T3 & T4 present low impedances when turned on into saturation & load CL will be

charged or discharged rapidly

 Output logic levels will be good & will be close to rail voltages since VCEsat is quite small & VBE  0.7V. Therefore, inverter has high noise margins

 Inverter has high input impedance, i.e., MOS gate input  Inverter has low output impedance

 Inverter has high drive capability but occupies a relatively small area

 However, this is not a good arrangement to implement since no discharge path exists for current from the base of either bipolar transistor when it is being turned off, i.e.,

 when Vin=Vdd,T2 is off and no conducting path to the base of T4 exists  when Vin=0, T1 is off and no conducting path to the base of T3 exists  This will slow down the action of the circuit

 The impedances Z1 and Z2 are necessary to remove the base charge of the bipolar transistors when they are being turned off. For instance, during a high-to-low transition on the input, T2 turns off first. To turn off T4, its base charge has to be removed. This happens through Z1. Adding these resistors not only reduces the transition times, but also has a positive effect on the power consumption. There exists a short period during the transition when both T3 and T4 are on simultaneously, thus creating a temporary current path between VDD and GND. The resulting current spike can be large and has a detrimental effect on both the power consumption and the supply noise. Therefore, turning off the devices as fast as possible is of utmost importance.

The conventional

BiCMOS Inverter

 Two additional enhancement-type nMOS devices have been added (T5 and T6).

 These transistors provide discharge paths for transistor base currents during turn-off. Without T5, the output low voltage cannot fall below the base to emitter voltage VBE of T3.

 Vin = 0 :

T1 is off. Therefore T3 is non-conducting T2 ON - supplies current to base of T4 T4 base voltage set to Vdd.

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Digital VLSI Design, ECE Dept.SET,JU. Page 3 T4 conducts & acts as current source to charge load CL towards Vdd.

Vout rises to Vdd - Vbe (of T4)

 Vin = Vdd : T2 is off

T1 is on and supplies current to the base of T3

T6 is turned on and clamps the base of T4 to GND. T4 is turned off. T3 conducts & acts as a current sink to discharge load CL towards 0V Vout falls to 0V+ VCEsat (of T3)

Again, this BiCMOS gate does not swing rail to rail. Hence some finite power is dissipated when driving another CMOS or BiCMOS gate. The leakage component of power dissipation can be reduced by varying the BiCMOS device parameters

Advantage:

 BiCMOS devices offer many advantages where high load current sinking and sourcing

is required. The high current gain of the NPN transistor greatly improves the output

drive capability of a conventional CMOS device.

 It follows that BiCMOS technology goes some way towards combining the virtues of both CMOS and Bipolar technologies.

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Digital VLSI Design, ECE Dept.SET,JU. Page 4  Design uses CMOS gates along with bipolar totem-pole stage where driving of high

capacitance loads is required.

 Improved speed over purely-CMOS technology

 Lower power dissipation than purely-bipolar technology (simplifying packaging and board requirements)

 Flexible I/Os (i.e., TTL, CMOS or ECL) – BiCMOS technology is well suited for I/O intensive applications. ECL, TTL and CMOS input and output levels can easily be generated with no speed or tracking consequences.

 Large circuits can impose severe performance penalties due to simultaneously switching noise, internal clock skews and high nodal capacitances in critical paths - BiCMOS

has demonstrated superiority over CMOS in all of these factors.

 High performance analogue  Latchup immunity

Main disadvantage:

 Greater process complexity compared to CMOS

 Results in a 1.25  1.4 times increase in die costs over conventional CMOS.

Taking into account packaging costs, the total manufacturing costs of supplying a BiCMOS chip ranges from 1.1 1.3 times that of CMOS.

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CMOS Processing Technology

CMOS processing steps can be broadly divided into two parts. Transistors are formed in the Front-End-of-Line (FEOL) phase, while wires are built in the Back-End-of-Line (BEOL) phase. This section examines the steps used through both phases of the manufacturing process.

Wafer Formation

The basic raw material used in CMOS fabs is a wafer or disk of silicon, roughly 75 mm to 300 mm in diameter and less than 1 mm thick. Wafers are cut from boules, cylindrical ingots of single-crystal silicon that have been pulled from a crucible of pure molten silicon. This is known as the Czochralski method and is currently the most common method for producing single-crystal material.

Photolithography

The regions of dopants, polysilicon, metal, and contacts are defined using masks. For instance, in places covered by the mask, ion implantation might not occur or the dielectric or metal layer might be left intact. In areas where the mask is absent, the implantation can occur, or

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Digital VLSI Design, ECE Dept.SET,JU. Page 6 dielectric or metal could be etched away. The patterning is achieved by a process called

photolithography

The primary method for defining areas of interest (i.e., where we want material to be present or absent) on a wafer is by the use of photoresists. The wafer is coated with the Photoresist and subjected to selective illumination through the photomask. A photomask is constructed with chromium (chrome) covered quartz glass. A UV light source is used to expose the Photoresist. Below Figure illustrates the lithography process.

The photomask has chrome where light should be blocked. The UV light floods the mask from the backside and passes through the clear sections of the mask to expose the organic Photoresist (PR) that has been coated on the wafer. A developer solvent is then used to dissolve the soluble exposed or unexposed Photoresist

Silicon Dioxide (SiO2)

Oxidation of silicon is achieved by heating silicon wafers in an oxidizing atmosphere.

The following are some common approaches:

 Wet oxidation––when the oxidizing atmosphere contains water vapor. The temperature is usually between 900 °C and 1000 °C. This is also called pyrogenic oxidation when a 2:1 mixture of hydrogen and oxygen is used. Wet oxidation is a rapid process.

Si+2H2O  SiO2+2H2

 Dry oxidation––when the oxidizing atmosphere is pure oxygen. Temperatures are in the

region of 1200 °C to achieve an acceptable growth rate. Dry oxidation forms a better quality oxide than wet oxidation. It is used to form thin, highly controlled gate oxides, while wet oxidation may be used to form thick field oxides.

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Digital VLSI Design, ECE Dept.SET,JU. Page 7 Si+O2  SiO2

CMOS TECHNOLOGIES

CMOS provides an inherently low power static circuit technology that has the capability of providing a lower-delay product than comparable design-rule nMOS or pMOS technologies. The four dominant CMOS technologies are:

 n-well process  P-well process  twin-tub process

 Silicon on Insulator process

The n-well process

A common approach to n-well CMOS fabrication is to start with moderately doped p-type substrate (wafer), create the n-p-type well for the p-channel devices, and build the n-channel transistor in the native p-substrate. The processing steps are,

Note: (Here I have not mentioned or drawn any Mask layer during this processing but in exam you have to mention)

Step1:

 Process starts with a moderately doped (1015 cm-3) p-type substrate (wafer)  An initial oxide layer is grown on the entire surface (barrier oxide)

Step2:

N-Well mask - defines the n-Well regions • Pattern the oxide

• Implant n-type impurity atoms (phosphorus) - 1016cm-3

• Drive-in the impurities (vertical but also lateral redistribution - limits the density ) Field

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Digital VLSI Design, ECE Dept.SET,JU. Page 8 Step3:

• Active area mask - define the regions in which MOS devices will be created

• LOCOS process to isolate NMOS and PMOS transistors

•

Grow gate oxide (dry oxidation) - only in the open area of active region

Step4:

• Polysilicon mask - define the gates of the MOS transistors

• Polysilicon is deposited over the entire wafer (CVD process) and doped (typically n-type) • Pattern the polysilicon in the dry (plasma) etching process

•

Etch the gate oxide

Step5: Thin oxide of 500Å

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Digital VLSI Design, ECE Dept.SET,JU. Page 9 • n-Select mask - define the n+ source/drain regions of NMOS transistors

• Define an ohmic contact to the n-well • Implant n-type impurity atoms (arsenic)

• Polysilicon layer protects transistor channel regions from the arsenic dopant

Step6:

• Complement of the n-select mask - define the p+ source/drain regions of PMOS transistors

• Define the ohmic contacts to the substrate • Implant p-type impurity atoms (boron)

•

Polisilicon layer protects transistor channel regions from the boron dopant

Step7:

• In the n-well two p+ and one n+ regions are created

• After source/drain implantation a short thermal process is performed (annealing): • moderate temperature

• drive the impurities deeper into the substrate • repair some of the crystal structure damage

• lateral diffusion under the gate: overlap capacitances

• Next the SiO2_{insulated layer is deposited over the entire wafer area using a CVD}

technique

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Digital VLSI Design, ECE Dept.SET,JU. Page 10 Step8:

• Contact mask - define the contact cuts in the insulating layer

•

Contacts to polysilicon must be made outside the gate region (avoid metal spikes throughthe poly and the thin gate oxide)

Step9:

• Metallization mask - define the interconnection pattern

• Aluminum is deposited over the entire wafer (evaporation) and selectively etched

•

The step coverage in this process is most critical (nonplanarity of the wafer surface)

•

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The twin-tub process:

Twin-tub CMOS technology provides the basis for separate optimization of the p-type and n-type transistors, thus making it possible for threshold voltage, body effect, and the gain associated with n-and p-devices to be independently optimized. Generally the starting material is either an n+ or p+ substrate with a lightly doped epitaxial or epi layer, which is used for protection against latch-up. The aim of epitaxy is to grow high purity silicon layers of controlled thickness with accurately determined dopant concentrations distributed homogeneously throughout the layer. The electrical properties for this layer are determined by the dopant and its concentration in the silicon. The process sequence, which is similar to the p-well process apart from the tub formation where both p-well and n-well are utilized.

The following steps  Tub formation  Thin oxide etching

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Digital VLSI Design, ECE Dept.SET,JU. Page 12  Contact cut definition

 Metallization.

Since this process provides separately optimized wells, better performance n-transistors (lower capacitance, less body effect) may be constructed when compared with a conventional p-well process. Similarly the p-transistors may be optimized. The use of threshold adjust steps is included in this process.

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Silicon on insulator process:

Silicon on insulator (SOI) CMOS processes has several potential advantages such as higher density, no latch-up problems, and lower parasitic capacitances. In the SOI process a thin layer of single crystal silicon film is epitaxial grown on an insulator such as sapphire or magnesium aluminate spinel. The steps involves are:

1) A thin film (7-8 μm) of very lightly doped n-type Si is grown over an insulator. Sapphire is a commonly used insulator.

2) An anisotropic etch is used to etch away the Si except where a diffusion area will be needed. 3) The p-islands are formed next by masking the n-islands with a photoresist. A p-type dopant

(boron) is then implanted. It is masked by the photoresist and at the unmasked islands. The p-islands will become the n-channel devices.

4) The p-islands are then covered with a photoresist and an n-type dopant, phosphorus, is implanted to form the n-islands. The n-islands will become the p-channel devices.

5) A thin gate oxide (500-600Å) is grown over all of the Si structures. This is normally done by thermal oxidation.

6) A polysilicon film is deposited over the oxide.

7) The polysilicon is then patterned by photomasking and is etched. This defines the polysilicon layer in the structure.

8) The next step is to form the n-doped source and drain of the n-channel devices in the p-islands. The n-island is covered with a photoresist and an n-type dopant (phosphorus) is implanted.

9) The p-channel devices are formed next by masking the p-islands and implanting a p-type dopant. The polysilicon over the gate of the n-islands will block the dopant from the gate, thus forming the p-channel devices

10) A layer of phosphorus glass is deposited over the entire structure. The glass is etched at contact cut locations. The metallization layer is formed. A final passivation layer of a phosphorus glass is deposited and etched over bonding pad locations.

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Digital VLSI Design, ECE Dept.SET,JU. Page 15 Due to the absence of wells, denser structures than bulk silicon can be obtained.

Low capacitances provide the basis of very fast circuits. No field-inversion problems exist.

No latch-up due to isolation of n- and p- transistors by insulating substrate. As there is no conducting substrate; there are no body effect problems Enhanced radiation tolerance.

But the drawback is due to absence of substrate diodes, the inputs are difficult to protect. As device gains are lower, I/O structures have to be larger. Single crystal sapphires are more expensive than silicon and processing techniques tend to be less developed than bulk silicon techniques.

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CMOS Process Enhancements

Note:(In this topic just know this and if question asked in exam just head lines are enough)

a) Using Multiple Threshold Voltages and Oxide Thicknesses b) Silicon on Insulator (SOI)

c) Using High-k Gate Dielectrics

 MOS transistors need high gate capacitance to attract charge to the channel. This leads to very thin SiO2 gate dielectrics (e.g., 10.5–12 Å, merely four atomic layers, in a 65 nm process)

 Gate leakage increases unacceptably below these thicknesses, which brings an end to classical scaling

 Simple SiO2 has a dielectric constant of k = 3.9, so gates could use thicker dielectrics and hence leak less if a material with a higher dielectric constant are available

 Example, Hafnium oxide (HfO2) has k 20.

d) Using Higher Mobility

 Increasing the mobility (u) of the semiconductor improves drive current and transistor speed. One way to improve the mobility is to introduce mechanical strain in the channel. This is called strained silicon.

e) Using Plastic Transistors

 MOS transistors can be fabricated with organic chemicals. These transistors show promise in active matrix displays, flexible electronic paper, and radio-frequency ID tags because the devices can be manufactured from an inexpensive chemical solution.

f) Using High-Voltage Transistors

 High-voltage MOSFETs can also be integrated onto conventional CMOS processes for switching and high-power applications. Gate oxide thickness and channel length have to be larger than usual to prevent breakdown.

g) Interconnect

 Interconnect has advanced rapidly. While two or three metal layers were once the norm, CMP has enabled inexpensive processes to include seven or more layers. Copper metal and low-k dielectrics are almost universal to reduce the resistance and capacitance of these wires.

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Digital VLSI Design, ECE Dept.SET,JU. Page 17 i. Copper Damascene Process While aluminum was long the interconnect metal of choice; copper has largely superseded it in nanometer processes. This is primarily due to the higher conductivity of copper compared to aluminum.

 Copper atoms diffuse into the silicon and dielectrics, destroying transistors.  The processing required to etch copper wires is tricky.

 Copper oxide forms readily and interferes with good contacts.

 Care has to be taken not to introduce copper into the environment as a pollutant.

 Barrier layers have to be used to prevent the copper from entering the silicon surface. A new metallization procedure called the damascene process was invented to form this barrier.

ii. Low-k Dielectrics SiO2 has a dielectric constant of k = 3.9–4.2. Low-k dielectrics between wires are attractive because they decrease the wire capacitance. This reduces wire delay, noise, and power consumption.

LAYOUT DESIGN RULES

Design rules include width rules and spacing rules. Mead and Conway developed a set of simplified scalable λ -based design rules, which are valid for a range of fabrication technologies. In these rules, the minimum feature size of a technology is characterized as 2 λ. All width and spacing rules are specified in terms of the parameter λ. suppose we have design rules that call for a minimum width of 2λ, and a minimum spacing of 3λ. If we select a 2 um technology (i.e., λ= 1 um), the above rules are translated to a minimum width of 2 um and a minimum spacing of 3 um. On the other hand, if a 1 um technology (i.e., λ= 0.5 um) is selected, then the same width and spacing rules are now specified as 1 um and 1.5 um, respectively.

LAMBDA RULE (λ=1um)

LAYER TYPE OF RULE VALUE

POLY

Minimum Spacing

2λ

Minimum Width

2λ

ACTIVE

Minimum Spacing

3λ

Minimum Width

3λ

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Digital VLSI Design, ECE Dept.SET,JU. Page 18 NSELECT/ PSELECT

Minimum Spacing

3λ

Minimum Width

3λ

METAL1

Minimum Spacing

3λ

Minimum Width

3λ

i. POLY

Minimum Spacing

2λ

Minimum Width

2λ

2λ 2λ

2λ

ii. ACTIVE

Minimum Spacing

3λ

Minimum Width

3λ

iii. METAL1

Minimum Spacing

3λ

Minimum Width

3λ

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3λ 3λ

3λ

iv. NWELL

Minimum Spacing

6λ

Minimum Width

10λ

Minimum Spacing between different layers

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Butting contact: The layers are butted together in such a way the two contact cuts become

contiguous. Metallization is used to establish the contact between poly and diffusion. We can better under the butting contact from figure

Poly

Metal1

Buried contact: The contact cut is made down each layer to be joined and it is shown

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MOSFET LAYOUT RULES

RULE

Meaning

VALUE

POLY Overlap

Minimum Extension over ACTIVE

2λ

POLY-ACTIVE

Minimum Spacing

1λ

MOSFET Width

Minimum N+/P+ MOSFET (W)

3λ

ACTIVE CONTACT

Exact Size

Minimum Space to Active Edge

2λ x 2λ

2λ

POLY CONTACT

Exact Size

Minimum Space to Active Edge

2λ x 2λ

2λ

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SCHEMATIC AND LAYOUT OF BASIC GATES using CMOS Logic

(

Note: Here I have not consider any design Rule while drawing Layout and also I left out Bulk/Body terminal in Layout)

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2.

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Digital VLSI Design, ECE Dept.SET,JU. Page 24 Implement the following using CMOS logic with minimum number of transistor and also draw Layout

3.

4. 5. 2- INPUT NAND

6. 2- INPUT NOR

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Latch up in Bulk CMOS

A byproduct of the Bulk CMOS structure is a pair of parasitic bipolar transistors. The collector of each BJT is connected to the base of the other transistor in a positive feedback structure. A phenomenon called latch up

It can occur when

(1) Both BJT's conduct, creating a low resistance path between VDD and GND

(2) The product of the gains of the two transistors in the feedback loop, beta1 x beta2, is greater than one.

The result of latch up is at the minimum a circuit malfunction, and in the worst case, the destruction of the device.

Cross section of parasitic transistors in Bulk CMOS

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Digital VLSI Design, ECE Dept.SET,JU. Page 26 Latch up may begin when Vout drops below GND due to a noise spike or an improper circuit hookup (Vout is the base of the lateral NPN Q2). If sufficient current flows through Rsub to turn on Q2 (I Rsub > 0.7 V), this will draw current through Rwell. If the voltage drop across Rwell is high enough, Q1 will also turn on, and a self-sustaining low resistance path between the power rails is formed. If the gains are such that beta1 x beta2 > 1, latch up may occur. Once latch up has begun, the only way to stop it is to reduce the current below a critical level, usually by removing power from the circuit.

The most likely place for latch up to occur is in pad drivers, where large voltage transients and large currents are present.

Preventing latch up(Fab/Design Approaches)

1. Reduce the gain product beta1 x beta2

o move n-well and n+ source/drain farther apart increases width of the base of Q2 and reduces gain beta2 also reduces circuit density

o buried n+ layer in well reduces gain beta1 of Q1

2. Reduce the well and substrate resistances, producing lower voltage drops o higher substrate doping level reduces Rsub

o reduce Rwell by making low resistance contact to GND

o Guard rings around p and/or n-well, with frequent contacts to the rings, reduces the parasitic resistances.

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Technology related CAD issues

The mask database is the interface between the semiconductor manufacturer and the chip designer. Two basic checks have to be completed to ensure that this description can be turned into a working chip.

 First, the specified geometric design rules must be obeyed.

 Second, the interrelationship of the masks must, upon passing through the manufacturing process, produce the correct interconnected set of circuit elements.  To check these two requirements, two basic CAD tools are required: a Design

Rule Check (DRC) program and a mask circuit extraction program.

a. Design Rule Checking (DRC)

Although we can design the physical layout in a certain set of mask layers, the actual masks used in fabrication can be derived from the original specification. Similarly, when we want a program to determine what we have designed by examining the interrelationship of the various mask layers, it may be necessary to determine various logical combinations between masks.

b. Circuit Extraction

Now imagine that we want to determine the electrical connectivity of a mask database.. An output statement might then be used to output the extracted transistors in some netlist format. The extracted netlist is often used to compare the layout against the intended schematic, Pre versus Post.

BASIC CIRCUIT DESIGN CONCEPTS

We have already seen that MOS structures are formed by the super imposition of a number conducting, insulating and transistor forming material. Now each of these layers has their own characteristics like capacitance and resistances. These fundamental components are required to estimate the performance of the system. These layers also have inductance characteristics that are important for I/O behavior but are usually neglected for on chip devices.

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Digital VLSI Design, ECE Dept.SET,JU. Page 28 The issues of prominence are

1. Resistance, capacitance and inductance calculations. 2. Delay estimations

3. Determination of conductor size for power and clock distribution 4. Power consumption 5. Charge sharing 6. Design margin 7. Reliability 8. Yield RESISTANCE ESTIMATION

Integrated Circuit (IC) chips contain many types of materials such as polysilicon, oxide, various diffusions of basic CMOS transistors, and metal. A popular resistor material is

polysilicon, also known as poly.

The concept of sheet resistance is being used to know the resistive behavior of the layers that go into formation of the MOS device. Let us consider a uniform slab of conducting material of the following characteristics.

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R - Resistance (ohms)

L - Length

W -width

-sheet resistivity (ohms-per-square)

 We know that the resistance is given by RAB= L/A.  The area of the slab considered above is given by A=Wt.

R

_AB

= L/Wt.

 If the slab is considered as a square then L=W. therefore RAB=/t which is called as sheet resistance represented by Rs.The unit of sheet resistance is ohm per square.

 It is to be noted that Rs is independent of the area of the slab. Hence we can conclude that a 1um per side square has the same resistance as that of 1cm per side square of the same material.

SHEET RESISTANCE OF MOS TRANSISTORS

2λ

The N transistor above is formed by a 2λ wide poly and 2λ n+ diffusion.  The L/W ratio is 1. Hence the transistor is a square,

 Therefore the resistance R is 1sqxRs ohm/sq i.e. R=1x104.  If L/W ratio is 4 then R = 4x104.

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Digital VLSI Design, ECE Dept.SET,JU. Page 30  If it is a P transistor then for L/W =1, the value of R is 2.5x104.

CAPACITANCE ESTIMATION

Parasitics capacitances are associated with the MOS device due to different layers that go into its formation. Interconnection capacitance can also be formed by the metal, diffusion and polysilicon in addition with the transistor and conductor resistance. All these capacitances actually define the switching speed of the MOS device.

Understanding the source of parasitics and their variation becomes a very essential part of the design specially when system performance is measured in terms of the speed. The various capacitances that are associated with the CMOS device are

1) Gate capacitance - due to other inputs connected to output of the device 2) Diffusion capacitance - Drain regions connected to the output

3) Routing capacitance- due to connections between output and other inputs

MOS Device Capacitance

The gate to channel capacitance formed due to the sio2 separation is the most profound of the mentioned three types. It is directly connected to the input and the output. The other capacitance

like the metal, poly can be evaluated against the substrate. The gate capacitance is therefore standardized so as to enable to move from one technology to the other conveniently.

The standard unit is denoted by Cg. It represents the capacitance between gate to channel with W=L=min feature size. Here is a figure showing the different capacitances that add up to give the total gate capacitance

Cgd, Cgs = gate to channel capacitance lumped at the source and drain Csb, Cdb = source and drain diffusion capacitance to substrate

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Digital VLSI Design, ECE Dept.SET,JU. Page 31 Cgb = gate to bulk capacitance

Total gate capacitance Cg = Cgd+Cgs+Cgb

Parameter Off Active Saturation

C gb Ɛo A t ox 0 0 C gs 0 Ɛo A 2 t ox 2Ɛo A 3 t ox C gd 0 Ɛo A 2 t ox 0 Ct= C gb+ C gs+ C gd Ɛo A t ox Ɛo A t ox 2Ɛo A 3 t ox

Area Capacitances of Layers

The fabrication process illustrates that the conducting layers are apparently separated from the substrate and other layers by the insulating layer leading to the formation of parallel capacitors. Since the silicon dioxide is the insulator knowing its thickness we can calculate the capacitance.

C=

Ɛ 

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

ins= relative permittivity of sio2=4.0 D= thickness of the dioxide in cm A = area of the plate in cm2

Standard unit of Capacitance Cg

It is convenient to employ a standard unit of capacitance that can be given a value appropriate to the technology but can also be used in calculations without associating it with an absolute value. the unit is denoted Cg and is defined the gate-to-channel capacitance of a MOS transistor having W=L=feature size, that is ,a ‘standard or ‘feature size’ of square.

Since the standard gate capacitance has been defined, the other capacitances like polysilicon, metal, diffusion can be expressed in terms of the same standard units so that the total capacitance can be obtained by simply adding all the values. In order to express in standard values the following steps must be followed,

1. Calculate the areas of area under consideration relative to that of standard gate i.e.4. (Standard gate varies according to the technology)

2. Multiply the obtained area by relative capacitance values tabulated.

3. This gives the value of the capacitance in the standard unit of capacitance Cg

4. Ratio= Relative area=

5. Capacitance = Relative area of Selected layer X Relative Capacitance of Selected layer

Problems

I. A particular layer of MOS circuit has a resistivity  of 1 ohm -cm. The section is 55um long, 5um wide and 1 um thick. Calculate the resistance and also find Rs

Solution:

R= RsxL/W, Rs= /t

Rs=1x10

-2

/1x10

6

=104ohm

R= 10

4

x55x10

-6

/5x10

6

=110k

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Digital VLSI Design, ECE Dept.SET,JU. Page 33 II. For a 5u technology the area of the minimum sized transistor is 5uX5u=25um2 i.e. λ=2.5u, hence, area of minimum sized transistor in lambda is 2λX2λ= 4λ2. Therefore for 2u or 1.2u or any other technology the area of a minimum sized transistor in lambda is 4λ2

Solution:

The figure above shows the dimensions and the interaction of different layers, for evaluating the total capacitance resulting so.

Three capacitance to be evaluated

Metal Cm, polysilicon Cp and gate capacitance Cg  Metal

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Digital VLSI Design, ECE Dept.SET,JU. Page 34 Area of minimum sized transistor in lambda is 2λX2λ= 4λ2.

Ratio= Relative area=

(

)

Relative area =300λ 2 /4λ2=75

Metal Capacitance = Relative area of Selected layer (i.e. Meta) X Relative Capacitance of metal Relative Capacitance of metal from table=0.075

Cm= 75 x0.075=5.625  Polysilicon

Area of Polysilicon= (4λx4λ+1λx2λ+2λX2λ)(excluding Gate region)

=22λ2 Relative area =22λ 2 /4λ2=5.5

Cp=5.5x0.1=0.55

 Gate

Area of Gate=2λX2λ= 4λ2

Relative area =4λ2 /4λ2=1(because it is a standard min size gate) Cg=1x1=1

Total capacitance Ct=Cm+Cp+Cg=5.625+0.55+1=7.2

Switching Characteristics

Charging and Discharging

The delay of the CMOS inverter is a performance metric for how fast the circuit is. This delay is dependent upon the RC charging or discharging of the load capacitor by the pMOS or nMOS devices respectively and provides a quantitative feel for the time that is taken by the output of the inverter to completely respond to a change at its input.

Rise time estimation:

In this analysis we assume that the p-device stays in saturation for entire charging period of load capacitor CL. The circuit may then be modeled as shown in below figure,

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Digital VLSI Design, ECE Dept.SET,JU. Page 35 The saturation current for P-transistor is given by

Idsp=

( | |)

This current charges CL and since its magnitude is approximately constant we have

V

out

=

∗

Substituting for Idsp and rearranging we have

t=

( )

We now assume that t=tr when vout=+VDD and |Vtp|=20%VDD=0.2VDD

After simplifying we get

t

r

=

This results compares reasonably well with a more detailed analysis in which the charging of CL is divided, more correctly, into two parts(1) saturation and (2) Resistive region of transistor.

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Fall time

Similar reasoning can be applied to the discharge of CL through n-transistor.the circuit model in this case is given as shown in below figure

Making similar assumption we may write for fall time:

t

f

=

Delay Time:

In MOS circuits, the delay of a single Gate is dominated by the output rise and fall time, the delay is approximately given by

t

dr

= t

r

/2

t

df

= t

f

/2

The average gate delay for rising edge and falling transitions is given by

t

_av

=(t

_dr

+t

_df

)/2

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Gate Transistor Sizing

Size the following logic with respect to INVERTER Gate Size

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2.

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