A New Low-Voltage, Low-Power and High-Slew Rate CMOS Unity-Gain Buffer

A New Low-Voltage, Low-Power and High-Slew Rate CMOS

Unity-Gain Buffer

M. Piry*, M. Khanjanimoaf* and P. Amiri* (C.A.)

Abstract: Class-AB circuits, which are capable of dealing with currents several orders of magnitude larger than their quiescent current, are good candidates for low-power and high slew-rate analog design. This paper presents a novel topology of a class AB Flipped Voltage Follower (FVF) that has better slew rate and the same power consumption as the conventional class-AB FVF buffer previously presented in literature. It is thus suitable for low-voltage and low-power stages requiring low bias currents. These buffers have been simulated using 0.5 µm CMOS Technology models provided by IBM. The buffer consumes 16 µA from a 0.9 V supply and has a bandwidth of 52 MHz with an 18 pF load. It has a slew rate of 10.3 V/µs and power consumption of 36 µw.

Keywords:Class-AB Circuits, CMOS Integrated Circuits, Flipped Voltage Follower, High Slew Rate Buffers,Level Shifting Techniques.

1 Introduction1

Voltage follower which is here denoted as VF, are widely used as output stages of opamps or in standalone configuration for signal conditioning, to accurately force an input voltage to an output load with both high input and low output impedance [1]. The conventional configuration of a VF is the voltage follower shown in Fig. 1-a. It has an output impedance of Rout = 1/gm (~ 2

kΩ) [2] and positive slew rate SR = ID2/CL. Notation CL

is the load capacitance, ID2, the drain current of

transistor M2 and gm, the small signal transconductance.

This VF is biased on the source side with a constant current source (M2) which ideally keeps a constant gate-to-source voltage in M1. This causes output voltage variations to follow the input voltage with a gate to source DC level shift. In practice this VF suffers from some problems like, not enough low output impedance, dependence of drain current of M1 on Iout and

nonsymmetrical slew rate.

The FVF [3] shown in Fig. 1-b is an improvement to a conventional VF. The FVF has a constant current through transistor M1, independent on the output current. Because of the shunt feedback [4], the output impedance is decreased to:

Iranian Journal of Electrical & Electronic Engineering, 2014. Paper first received 7 Aug. 2013 and in revised form 1 Oct. 2013. * The Authors are with the Department of Electrical Engineering, Shahid Rajaee Teacher Training University, Tehran, Iran.

E-mails: Piry.milad@yahoo.com, m_khanjani69@yahoo.com and pamiri@srttu.edu.

o m m o m o out

r g g r g r

R ₂

1 1 2 2

1

) 1

( 1

1 _≅

+ + =

(1)

It is much smaller than Rout of conventional VF. The

voltage gain is almost unity:

1 2 1 2

1 2 1 2 2 2 1

o o m m

o

i o o m m o m

r r g g V

V =r r g g +r g + (2)

This is bigger than the voltage gain of conventional VF. The circuit in Fig. 1-b is able to source a large current but its sinking capability is limited by the drain current of M3.

To overcome this problem, circuit in Fig. 1-c [5-7] is used. Under quiescent conditions, every transistor is in saturation region and no current is delivered to the load. Neglecting second order effects, transistor M4 copies the drain current of transistor M1. Therefore the total current taken from the supply voltage is 2Ib ( = 2ID3)

which increases the power consumption of the circuit. In this paper a very simple, low-voltage class-AB structure is proposed which is able to take current from supply sources only when the load requires it, so the power consumption decreases, and the slew rate increases, thus it can be used in voltage and low-power amplifiers as a level shifter [8].

The proposed structure has been simulated using the models of the IBM CMOS 0.5 µm technology, in order to compare its performance with the other buffers in terms of settling time, bandwidth, output impedance, power consumption and total harmonic distortion.

Fig. 1 Unity-G (c) Class-AB F

2 A New C The new and sink a m quiescent cur

When the the output v transistor M biased by th voltage rises M2, and lea region. In thi ID3, and the o

2 1 out o R g r = + When the voltage of t transistor ten through trans voltage decre off region an In this opera equals to I approximatel

(a)

Gain buffers: (a FVF [7].

Class-AB Unit unity-gain bu maximum cur rrent, as it wil e input signal voltage Vo, t

M1 tends to d he current so s, forcing a la ading the tra is operation re output impeda

2 1 1

1

(1 )

m o m

g +r g e input signal transistor M1 nds to the o sistor M1 is fi eases, leading nd transistor M

ation regime ID3+ID4, and

ly given by:

(

(c)

a) Conventiona

ty Gain Buffe uffer in Fig. 2 rrent which i ll be shown ne l Vin increases

the source-to-decrease. As ource M3, its arge current th

ansistor M4 egime the outp ance is given b

)

l decreases, th 1 tends to in ohmic region.

ixed by M3, it g the transistor M4 into the s the current w

the output (b)

al VF. (b) FVF

er

is able to sou is larger than ext.

s, with respec -gate voltage transistor M1 s drain-to-sou hrough transi

into the cut-put current is by:

he source-to-g ncrease and

As the curr ts source-to-dr r M2 into the c saturation regi which is sink t impedance [3]. urce n its ct to e of 1 is urce stor -off ID2

(3) gate this rent rain cut-ion. king is o R sig vol Fig tran G V cur vol tran D V shi (6) D V sho vol to k i V sho i V the reg edg vol lea sho and gat var ma the flo 3-c tran cap C 4 4 1 out m o g r = + Thus transist gnal decreases ltage in quies g. 1-b.

In quiescent nsistor M4 is

4

GS =VDD−VSG

In Eq. (5), rrent of trans ltage should nsistor M4. T

N

DD−VSS =Vth

To decrease ifter shown in ) is given by:

N

DD−VSS =Vth

One basic im own in Fig. 3 ltage of transi keep M1 in sa

2 | V p

G th

V

≥ −

To keep M ould be satisfi

2

G L

V V V

≥ + −

From Eqs. (8 e input signal gion before th

If the input ge, the gate v ltage is shifted ads transistor ows the variat d M4. In Fig. te voltage of riations of ga aximum drain e negative slew

A better te oating voltage c. In quiesc nsistor M4 i pacitor C is eq

and the resis

1 1

1

(1+r g_{o m})

tor M4 sinks c s, so the curr

scent conditio

conditions, th given by:

2

G −VSS =VDD

k2 is 1 2

PC L μ

sistor M4 nea be near th Thus the Eq. (5

2 2 P D th I V k + + the required n Fig. 3-a is u

2 2 P D th I V k + + mplementation 3-b, in which istor M5. The aturation is giv

|

M4 in saturati ied:

1 N

SG th

V −V 8) and (9), w

leads the tra e transistor M

signal is a sq voltage of tra

d to a higher v M6 into the tions of gate 4-a a limitati transistor M4 ate voltage o n current of tr w rate decreas echnique for

source is disc ent condition s equal to V qual to VC−VG

stor R form a

current only w rent taken fro

ons is lower

he gate-to-sour 2 2 P D th I V k − − OX C W

L . To ke

ar zero, its g he threshold 5) is given by:

P

supply voltag used. In this c

P −VL

n of this DC l h VL is the s minimum vol ven by:

ion region, c

e conclude th ansistor M1 in M4.

quare wave, ansistor M2 in

value by trans e cut-off reg

voltages of tr ion can be ob 4 cannot exact f transistor M ransistor M4 ses.

implementa cussed in [9], ns, the gate VC and the v

2

G L

V =V . Since

a high pass c

(4)

when the input m the supply than FVF in

rce voltage of

SS

V

− (5)

eep the drain gate-to-source d voltage of

:

(6)

ge, a DC level circuit the Eq.

(7)

evel shifter is source-to-gate ltage required (8) condition (9) (9) hat decreasing

nto the ohmic

in the falling ncreases, this sistor M5 and ion. Fig. 4-a ransistors M2 bserved as the tly follow the M2. Thus the is limited, so

ation of this shown in Fig. e voltage of oltage across e the capacitor circuit with a t y n f n e f l . s e d ) g c g s d a 2 e e e o s . f s r a

corner frequ

lower 3 dB should have of integrated

3dBLOW 100

f <

large resisto capacitance amplifier. E resistor is di circuit, unde transistors M region. So combination quiescent co keep M5 and large effectiv In the cir of transistor transistors M Thus this ci before, and th

If we use structure lik although the improves, be sourcing lar capability of and M10 imp current of rig

3 Simulatio The struc Fig. 5) and c for comparis CL = 18 pF.

parameters p were used threshold vo respectively. µA. All the d of transistors

Fig. 2 Basic im

ency f3dBLOW

frequency as extremely larg d capacitors 0Hz, R shoul

or would ha that would Efficient impl iscussed in [1 er dynamic M5 and M6 are

the equivale of these tran onditions the

d M6 in sub-th ve resistance. rcuit of Fig. 3 M4 follow t M2 exactly, as ircuit overcom

he negative sl e the circuit ke the confi power consum ecause the righ

rge currents f sinking large

prove the capa ght and left cir

on Results ctures of pro class-AB FVF son with VDD

For simulatio provided by

that have n oltages VthN =

The biasing devices used h s are reported

mplementation 1 2πRC

= , in

s low as pos ge values. Sin are in the p ld be larger th ave large are

limit the ba lementation o 0], shown in conditions, o e on, and the o ent resistance nsistors is ve control volta hreshold regio

-d, the gate v the gate volta s can be obse mes the limit lew rate is imp

in Fig. 3-d a iguration sho mption increa

ht circuit has and the le e currents, als ability of sink rcuits respecti

oposed buffer F [7] (Fig. 1-c = 0.45 V, V ons 0.5 µm CM

IBM (techn nominal NMO = 0.67 V and

current sourc have 0.6 µm

in Table 1.

of proposed cir

n order to set

ssible, resistor nce typical val pF range, to han 1 GΩ. Suc ea and paras andwidth of of such a la Fig. 3-d. In only one of other is in cut-e of thcut-e scut-e ery large. Un ges Vb2 and

on to have a v

voltage variati age variations

rved in Fig. 4 tation mentio proved. and its P-chan own in Fig. ases, the slew r

the capability ft one has so transistors king and sourc

ively.

s (Fig. 3-d) c) were simula

SS = -0.45 V

MOS technolo nology: SIGE

OS and PM d |VthP| = 0.5

ce is equal to length. The si

rcuit.

the

r R lues

set ch a sitic the arge this the -off ries nder Vb3

very

ions s of 4-b. ned

nnel 5, rate y of the M4 cing

and ated and ogy E05) MOS 5 V o 20 izes

Fig

lev bas bas

(a)

(b)

(c)

(d)

g. 3 Proposed c vel shifter impl sed on [10]. (d sed on [10].

circuit: (a) impr lemented by tra d) large resisto

roved by level ansistor. (c) D or implemented

shifter. (b) DC DC level shifter d by transistor C

r r

Fig. 4 Gate vo

Fig. 5 Improve

Fig. 6 buffers.The mVPP swing

the negative 5, 5.4 V/µs f the circuit of negative slew 2.7, 6.1 V/µs

Fig. 7 sh all FVFs. T frequencies. bandwidth of a capacitor lo Fig. 8 sh obtained by buffer’s outp voltage in th impedance. I impedance o

Fig. 9 sh 200 mV pe measured TH sinusoidal i respectively.

oltage variations

ed voltage buff

shows the s input step sig and frequency slew rate of 1 for the circuit f Fig. 1-c. Th w rate. Also t s respectively. hows the frequ They are cha It can be ob f 51.5, 40.3 an oad of 18 pF.

ows a compar applying a 1 put terminals his case corre It can be seen f 161, 299, 22 hows the mea eak-to-peak si HD for a 1 input signal

(a)

s of transistors

fer.

step respons gnals of the b

y of 1 MHz. T 0.3 V/µs for t t of Fig. 3-d a hat it agrees w the positive s .

uency respons aracterized by bserved that t nd 53.7 MHz r

rison of the o 1 A AC curre with the inpu esponds exact n that the circ 20 Ω respectiv asured respon

inusoidal inp MHz, 200 m

was -50.4,

M2 (continuou

e of the th buffers have 4 This figure sho the circuit of F and 6.1 V/µs with the expec slew rate is 10

se comparison y similar 3 the circuits h respectively w

output impeda ent source to ut grounded. T

tly to the out cuits have out vely.

se for a 5 M put voltage. T mV peak-to-p

-45, -54.9

us line) and M4

hree 400 ows Fig. for cted 0.3,

n of dB have with

ance the The tput tput

MHz, The peak dB

200 rep cap dra the 550 the

be con of

Ta

(dotted line): (a

In Fig. 10 th 0 mV squa presented curr pacitor. It ca ained from loa e maximum c

0, 65 and 140 e circuit of Fig Fig. 11 show observed tha nstant in the la

Fig. 1-c.

ble 1 Sizes of t

MOS Width (µm)

0.6 4 6 8 14 17 70

(b)

a) circuit 3(b). (

he simulated o are input si rent is the on an be seen th ad capacitor is current source 0 µA. It can be

g. 5 is improve ws the gain v at the gain of arger input vo

transistors.

Fig. 5

M5,M6,M11, M3,M7 M4 M2 M1,M9,M

- M10

(b) circuit 3(d).

output current ignal is pre ne going thro hat the maxi s 304, 251 and ed to the load e seen why th ed.

versus input v second propo oltage range th

Fig. 3-d

M12 M5,M6 M3 M4 M2 M8 M1

- -

.

for a 1 MHz, esented. The ough the load imum current d 217 µA and d capacitor is he slew rate in

voltage. It can osed circuit is han the circuit

d Fig. 1-c

6 - M3

- - M1,M4

M2 -

, e d t d s n

n s t

Fig. 6 Step res

Fig. 7 Frequen

Fig. 8 Output

Fig. 9 Output

sponse of three

ncy response of

impedance of b

of the buffers w buffers.

f buffers.

buffers.

with 0.2 VPP 1 MMHz input.

Fig

squ

Fig

und fro 0.1 0.0 Th 68 pro cla

mix cir CM is per

4

ban neg TH (sle

in sle c in alth

g. 10 Simulated uare input signa

g. 11 DC gain o

Note that th der temperatu om -50 °C to 1 1 dB for the 01 dB for the f he bandwidth i MHz to 17 oposed circuit ass-AB FVF is Since VLSI xed-signal ci cuits are integ MOS technolo critical subje rformed in fut

Comparison Table 2 pres ndwidth, stat gative slew r HD, HD2, HD3

ew rate*CL)/P

It can be see circuit of Fig ew rate is high

n compliment hough the slew

d output curre al.

of buffers vs. inp

he proposed ure variations 120 °C, the low

second propo first proposed is reduced fro 7 MHz for t respectively s reduced from

technology m ircuits on a grated with an ogy scales dow

ect for propo ture.

n of Buffers ents a compar tic power co rate, output

3 and FOM

.

Power. en that, althou

. 5 is equal to hly improved. tary configura w rate enhanc

nt with a 1 M

put voltage.

buffers are s: varying the w-frequency g osed circuit a d circuit and cl om 77 MHz to the second a y. While the b m 91 MHz to 2 makes it pos

single die w nalog blocks [

wn [12, 13], n osed circuits

rison of buffe onsumption,

impedance, v Note that FOM

ugh the power o the circuit of

If we use circ ation like circ ces, the power

MHz 200 mVPP

rather stable e temperature gain varies by and varies by lass-AB FVF. o 33 MHz and and the first bandwidth of 27 MHz. sible to have where digital 11] and as the noise analysis that will be

ers in terms of positive and voltage gain, M is equal to

r consumption f Fig. 1-c, the cuit of Fig. 1-cuit of Fig. 5, r consumption

P

e e y y . d t f

e l e s e

f d , o

n e -, n

increases to 72 µW, which is 30 µW larger than power consumption of circuit Fig. 5. Note that since in these circuits, transistors are operation in strong inversion they are not capable to operate under ultra-low-power application [13]. The bandwidth of second proposed circuit is larger than other buffer configurations presented in literature except the buffer Fig. 1-c. Thus it can be used in high frequencies. Also it can be seen that the second proposed circuit has the largest FOM among Fig. 3-d and Fig. 1-c.

5 Conclusion

A new class-AB unity-gain buffer based on the Flipped Voltage Follower (FVF) has been proposed. This circuit can be operated at a low voltage and low power. With respect to other class-AB stages based on the FVF topology, it has superior slew rate with low power consumption. This novel buffer has also low output impedance. The characteristics of the proposed circuit were validated by simulations.

Table 2 Comparison of buffers.

Circuit Technology Voltage _Supply ID

(µA) (µw)P BW SR

+

(V/µs) SR

-( V/µs) FOM

Rout

(Ω) Gain (dB) THD (dB)HD2 HD(dB)3

Fig. 5 Second proposed

circuit

0.5 µm 0.9 V 16 36 _C76 MHz

L=10 pF 10.3 10.3 0.28 210 -0.35 -50 dB 200 mVPP

1 MHz -53 -54

Fig. 3-d First proposed

circuit

0.5 µm 0.9 V 16 18 _C68 MHz

L=10 pF 2.7 5.4 0.23 489 -0.2 -45 dB 200 mVPP

1 MHz

-45 -60

Fig. 1-c

Class-AB [7] 0.5 µm 1.5 V 20 36

87 MHz

CL=10 pF 6.1 6.1 0.17 220 -0.2 -55 dB 200 mVPP

1 MHz -56 -62

Buffer [1] 65 nm 1.2 V 10 - 100 MHz_C

L=2 pF - - - 760 -0.4 - - -

FVF [3] 65 nm 1.2 V 7.8 - _C30 MHz

L=2 pF - - - 540

-0.6 _{- - -}

SDP [5] 0.5 µm 3 V 30 - _C11 MHz

L=10 pF - - - 2K - -59 dB 300 mVPP

2 MHz

- -

DFVF [5] 0.5 µm 3 V 30 - _C70 MHz

L=10 pF - - - 40 -

-52 dB 300 mVPP

2 MHz - -

CASDPFVF

[5] 0.5 µm 3 V 30 -

70 MHz

CL=10 pF - - - 0.5 - -52 dB 300 mVPP

2 MHz

- -

References

[1] F. Centrurelli, P. Monsurro and A. Trifiletti, “A Class-AB Flipped Voltage Follower Output Stage”, IEEE (2011) 20th European Conference on Circuit Theory and Dedsing (ECCTD), pp. 757-760, Aug. 2011.

[2] B. Razavi, Design of Analog CMOS Integrated Circuits, New York: McGraw-Hill, 2001.

[3] R.G. Carvajal, J. Ramirez-Angulo, A. Lopez-Martin, A. Torralba, J. Galhn, A. Carlosena and F. Mufioz, “The Flipped Voltage Follower: A useful cell for low-voltage low-power circuit design”, IEEE Transactions on Circuits and Systems I, Vol. 52, No. 7, pp. 1276-1291, July 2005.

[4] H. Faraj Baghtash, S. J. Azhari and Kh. Monfaredi, "A Novel Very High Performance CMOS Current Mirror With Extremely Low Input and Ultra High Output Resistance", Iranian

Journal of Electrical & Electronic Engineering, Vol. 7, No. 4, pp. 235-240, Dec. 2011.

[5] J. Ramirez-Angulo, S. Gupta and R. G. Carvajal, “New Improved CMOS Class-AB Buffers Based on Differential Flipped Voltage Followers”, IEEE International Symposium on Circuits and Systems, May 2006.

[6] J. Ramirez-Angulo, S. Gupta and R. G. Carvajal, A. Torralba, M. Jimenez and F. Munoz, “Comparison of Conventional and New Flipped Voltage Structures with Increased Input/output Signal Swing and Current Sourcing/Sinking Capabilities”, IEEE International Symposium on Circuits and Systems, Vol. 2, pp. 1151-1154,Aug. 2006.

[7] M. Jimenez, A. Torralba, R. G. Carvajal and J. Ramirez-Angulo, “A new low-voltage CMOS unity-gain buffer”, IEEE Int. Symposium on Circuits and Systems, May 2006.

[8] S. H. Mirhosseini and A. Ayatollahi, "A Low-Voltage, Low-Power, Tow-Stage Amplifier for Switched-Capacitor Application in 90 nm CMOS Process", Iranian Journal of Electrical & Electronic Engineering, Vol. 6, No. 4, pp. 199-204, Dec. 2010.

[9] J. Ramirez-Angulo, M. S. Sawant, R. G. Carvajal and A. J. Lopez-Martin, “Cascode Mirrors and Telescopic Op-Amps”, IEEE Int. Symposium on Circuits and systems, May 2006.

[10] M. Bikumandla, J. Ramirez-Angulo, C. Urquidi, R. G. Carvajal and A. J. Lopez-Martin, “Biasing CMOS amplifiers using MOS transistors in sub-threshold region”, IEICE Electronics Express, Vol. 1, No. 12, pp. 339-345, Sep. 25, 2004.

[11] G. Khodabandehloo, S. Mirzakuchaki and G. Karimi, “Modeling and Simulation of Substrate Noise in Mixed-Signal”, Iranian Journal of Electrical & Electronic Engineering, Vol. 2, No. 1, pp. 8-15, Jan. 2006.

[12] R. Mirzalou, A. Nabavi and Gh. Darvish, “A Highly Linear LNA with Noise Cancellation for 5.8-10.6 GHz UWB Receivers”, Iranian Journal of Electrical & Electronic Engineering, Vol. 8, No. 3, pp. 234-242,Sept. 2012.

[13] E. Farshidi, "A Micropower Current-Mode Euclidean Distance Calculator for Pattern Recognition”, Iranian Journal of Electrical & Electronic Engineering, Vol. 5, No. 1, pp. 42-50, March 2009.

Milad Piry was born in 1990 in Tehran. He received the electrical engineering in 2013 from Shahid Rajaee Teacher Training University (SRTTU Tehran, Iran). He is currently pursuing his education to get MS. degree in Sharif University of Technology in Microelectronics. His research interest is to design low- voltage and low-power analog integrated circuits, especially the design of operational amplifiers.

Mona Khanjanimoaf was born in 1991 in Bandar-e Anzali. She received the electrical engineering in 2013 from Shahid Rajaee Teacher Training University (SRTTU Tehran, Iran). Her research interest is to design Analog integrated circuit, especially the design of low-voltage and low-power circuits.

Parviz Amiri was born in 1970, received B.S degree from University of Mazandaran in 1994, M.S from Khajeh Nasir Toosi University (KNTU Tehran, Iran) in 1997, and his Ph.D. from University of Tarbiat Modares (TMU Tehran, Iran) (2010), all degrees in electrial engineering (electronic). His main research internest include electronic circuit design in industries. His primaryresearch interest is RF and power circuit design. He is currently with the department of electrical engineering Shahid Rajaee Teacher Trainning University in Tehran, Iran.