std sasi1 pdf

(1)

tDlEX

'"

STD-SASI1

(J[]

1"

FEATURES

o STD-Z80 Bus Compatible o 4 MHz Operation

o Supports Shugart Associates Systems Interface (SASI)

o Auto Handshake Logic o Polled or Interrupt Driven

o 1/0 Addressing on 4 Byte Boundary o IOEXP Supported

o

+

5 Volt only o 1 year warranty

DESCRIPTION

The Colex STD-SASIl is designed to in-terface to the Shugart Associates System Interface

T:

This interface is designed to allow users at a system level to connect mass storage peripherals without affec-ing software. The STD-SASIl implements the host adapter on the STD Bus. This interface is the standard for Winchester 5% inch disk subsystems. The STD-SASIl can operate in either a polled or interrupt transfer mode.

The STD-SASIl consists of two major parts, a parallel data port and auto hand-shaking logic. This port is designed with a 3881 PIO chip. Port A is designated for data and will accept bi-directional infor-mation transfers. Port B is designated for status and control. The status signals are inputs, the control signals are outputs from the port. AU signals are fully buff-ered to and from the PIO.

The STD-SASIl will fully support Z-80 mode 2 interrupts as well as polled oper-ation. The board also has an external con-nector JA allowing DMA operation. A twisted pair wire can be run from JA to the Colex STD-FLP2 card. The output sig-nals an external READY output from this card. Both commands, data and status may be DMA'd to or from the

STD-SASIl.

Automatic handshaking is supported. Jumper J3 enables a circuit that asserts the SASI ACK (acknowledge) signal after reading or writing to the SASI Bus. This provides an increase in throughput since software does not have to toggle the ACK control line.

'"Trademark of Shugart Associates

COLEX AMERICA. INC PO Box 801462, Dallas, Texas 75380. Un,ted States 214/458.2779 COLEX UK. LTD Index House. Ascot Berks, ~L57EU, England, [Q99OJ-23377

COLEX ASIA PACIFIC Luk Hop Industrial Bldg, 15th Floor. 8 Luk Hop St , San Po Kong, Kowloon. Hong Kong 3/7265651

(2)

S10 BUS

SPECIFICATIONS

ELECTRICAL

~ )

A(loress

Decooe

ana

Data Huller"

i

Address Select

,2

o System clock: 4.0 MHz

o Data bus: 8 bits, bi-directional

o Address bus: 16 bits

o Signal Loading: Inputs: One 74LS

maximum

Outputs: - 3mA min

(a 2.4 volts

24mA min (i:/ 0.5 volts

o Operating Temperature: O°C to 60°C

o System Interrupt Units: 1 SIU

o Interrupts: All three Z80 modes

o Power Requirements:

MECHANCIAL

o Card Dimensions:

Pori A

Form Factor H W L Units

STD-Bus

I

0.60

I

4.5 6.5

I

inches

I

o PC Board thickness: 0.062 inches

o Connectors:

STD-Bus (1):

SAS[ Bus (JB):

Ext. Ready (JA):

56 pin dual readout; 0.125 inch centers

50 pins; 0.100 inch

centers

2 pin; 0.100 inch

centers

SASI BUS

JB

rml

~

JA

ORDERING INFORMATION

Part Number STD-SASIl

STM-SASIl

Description

STD-SASI Bus Interface

Card

STD-SASll Technical Manual

I-~~~"'-.. ~ T ~~,;.o., 1I""--:-'1j~:-"'l'''I -J-_·--,....-!'!""~T·-~-I ... l~\ ,.~ - ' ,

. Colex reserves the right to make changes to the circUitry or specifications without notice

. :", '" ;. __ ~ .. ',=-r.1-":..:..:.Colex and the Colex logo are trademarks of Colex Amertca. Inc

:. - ,.. . I :. c'''~~~-;;~Colex America, 1983 Prtnted In U S.A All rtghts Reserved Rev 1.1

(3)

,

FEATURES

o

SlD-Z80 Bus Compatible

o

Supports Shugart Associates

Systems Interface (SASO

o

Auto Handshake Logic

o

Polled or Interrupt Driven

o

[/0 Address on 4 Byte Boundary

o

[OEXP Supported

o

4

MHz Operation

o

Single

+5

Volt Supply

o

I Year Warranty

DESCRIPTION

The Colex STD-SASII is designed to inter-face to the Shugart Associates System Interinter-face ' •.

This interface is designed to allow users at a system

level to connect mass storage peripherals without affecting software. The STD-SASII implements the host adapter on the STD Bus. This interface is

the standard for Winchester

5 1/4

inch disk

sub-systems. The STD-SASII can operate in either a polled or interrupt transfer mode.

The STD-SASII consists of two major parts: a parallel data port and status control logic. This

port is designed with a 3881 Pia chip. Port A is

designated for data and will accept bi-directional information transfers. Port B is designated for sta-tus and control. The stasta-tus signals are inputs; the control signals are outputs from the port. All signals are fully buffered to and from the P[O.

. The STD-SASII will fully support Z 80

mode

Z

interrupts as well as polled operation. The

board also has an external connector JA allowing

STD-SAS11

- - " , - - -

-SASI1

STD-SASII

DMA operation. A twisted pair wire can be run from JA to the DMA on board the COLEX STD-FLPZ card. The output signals an external

READY output to the DMA which controls

a

read

or write operation. Both commands, data and sta-tus may be DMA'd to or from the STD-SAS[1.

Automatic hilOdshaking is supported Jumpet)3 enables a circuit that asserts the SAS[ ACK

(Acknowledge) signal after reading or writing to the SASI Bus. This provides an increase in throughput since software does not have to toggle the ACK control line.

, M

Trademark of Shugart

Associates

Page I

•

(4)

,

Address Port A STD- Decode

BUS and

Data Bullers

H

IH

3881-4 PIO

'rl

_.

_IH

Port B

I I

I

Address Select

J2

Figure 2_ Block Diagram of STD-SASII

liD

ADDRESSING

The STD-SASII is addressed on any 4 byte boundary_ The address selection is made using)2 with 6 address lines, A2-A 7 and 10EXP. Insertion of a jumper selects a logic zero, no jumper selects a logic L For example, to select I/O port OOH, with

10EXP active low, all jumpers must

be

installed

STO-SAIl

'I

Data

V

,

SASt , BUS

[>

Control ,

•

Status

<J

JB

rr::J.

EXT.

~ DMA

JA

Address line j2 Pin Pairs ' Sel~ct 100" i Selecl .t I" A7 13-14 jumpered Open A6 11-12 jumpered Open

A5 9-10 jumpered Open

•

A4 7-8 , jumpered Open

A3 5-6 jumpered Open

Al H jumpered Open

I !IOEXP 1-2 jumpered Open

Figure 3. Address Srrapping Options

[image:4.602.17.556.29.467.2]

(5)

. PORT UTILIZATION

The PIO on-board the STD-SASli responds to four sequential port addresses. These four port , addresses control data flow, set-up, and interrupt

Initialization. Below is the base address map for the PIO Data and Control Registers.

A7·Al AI AO ; Description

..

X 0

,:

0 . PortA Data

X 0 I Port B Data

X I 0 ' Port A Control

X I I . Port B Control

Figure 4. Port Utilization

Port A is the bi-directional data port The data is

buffered by bi-directional transceivers connecting the

SASI Bus. Port B data is connected to the eight SASI Bus control and status signals. The PIO register designation is as follows:

. Port ₇ ₆ ₅ ₄ _J ₂ _I _:0

A Data 'D7

106

IDS 104 !DJ D2 DI

DO

[image:5.611.28.575.45.846.2]

B Data RES ISEL lACK IBSY :MSG c/D REQ 1110

Figure

5.

SASI Data Port Definition

The Port A and Port B control registers are used

for PIO initialization. .

STO-SASI1

:

JAc;:!J I : : . . :

I f 1 JB

, ,

LUJ

J3

"

~~6elor?u

[ooooooo!J2

1 0 0 0 0 0 0 0 1

123'561)

Figure

6.

Connectors and Header Locations

HEADER

]l

AUTO ACKNOWLEDGE ENABLE

•

j I is the Auto Acknowledge Enable which selects

the Auto Acknowledge logic. Insertion of a jumper

enables this logic. Typically a system is used with this •

option enabled

CONNECTORS

JA EXTERNAL READY OUTPUT

This is an active HIGH signal which may be connected to an external DMA board External Ready goes HIGH when th is REQ (request) signal goes low, which signals that data is available on the SASI Data

Bus. Clearing of External Ready occurs by reading from •

. the STD·SASli data port. Pin 2 of the connector

is an 74LS TTL signal; pin I is ground. '

(6)

.,

JB SASI BUS

Figure 7 shows the symbol, direction and func-tion of the pins of JB, the 50-pin connector for the SASI Bus. The odd pins (I, 3, 5, ... ) are all grounded, the even pins active or unused. Interconnect is made typically with a 50-pin ribbon cable.

Pin No. Symbol ! Direction Function

2 DBO

I

_,

Bi-directional Data Bit 0 4 OBI Bi·direcrional _{Data Bit I} 6 DB2 Bi-directional Data Bit 2 8 DB3 Bi-directional Data Bit 3

10 OM Bi-directional Darn. Bit-4

12 DB5 Bi-direc'tional Data Bit 5

14 DB6 Bi-directional Data Bit 6 16 DB7 1 Bi-directional Data Bit 7

18

'N/C

! _-

-20

N/C

_!

-

-Z2

N/C

:

_-

-Z4

N/C

_i

_-

-26

N/C

I

.

-

-28

N/C

i

_,

_-

-30

N/C

,

I

_-

-32

N/C

_I

_-

.

-34

N/C

I ,

i

-

-36 BSY Input _{Controller Busy} 38 ACK Output . Request Acknowledge 40 RST

,

Output Reset Controller

42 MSG I

Input Complete Message

44 SCL.

I

Output Select Controller

46 ClD ! I· Input Comm.1ndlDatn Mode 48

REQ

J

Input Request Acknowledge 50

. vo

!

Input Data Direction

Figure 7. SASI

Bus

Signal Definitions

STD-SAS11

-

,

'SPECIFICATIONS

o

System clock: 4.0 MHz

o

Data Bus: 8 bits, bi-directional

o

Address Bus: 16 bits

o

Signal Loading: Inputs: One 74LS maximum

Outputs: IOH='-3mA min @

2.4 volts

. IOL =24mA @ 0.5 volts

o

Operating T emperatute:

O°C

to

60°C

o

System Interrupt Units: 1 SIU

o

Interrupts: All three ZSO modes

o

Power Requirements: @ 25· C

Parameter ~ Condition , Min. _{: Typ.} i Max. : Units

Vee

, -

4.75 5.0 .5.25 ' Volts Icc @5.0V

-

355 : 600 rnA

MECHANICAL

o

Card Dimensions:

Form Factor ,H W ,L i Units

STD-Bus 0.60 4.5 .6.5 1 inches

.0

PC Board thickness: 0.062 inches

o

Connectors:

STD-Bus UI): 56-pin dual readou~ 0.12 inch

•

centers •

SASI Bus UB): 50 pins; 0.100 inch centers Ext Ready UA): 2-pin; 0.100 inch centers

[image:6.602.42.544.28.851.2]

(7)

,

•

Q

U

"

C

~

«

• '"

oj

a:

• !

0 I

£1

.

_g

0·

~

I

"- i!

01'

\

~

_...

₁ _g

V)

i

,~

,

«

_i

~

V) 0

,

'

, ,

f- !~ ! !

i

CI V) _•

f

_U~

₃₁

I

•

N

:;

•

A

,

•

(

;;

~

rl'

_!I

_!

_I

!

ti

_iii •

,

.

~

:f-'!t-

"

~~!-

_u

\~r

8n):;

_t

• .

-

.

;

(~

₅₁

₄

_P

';i

_,.'>

.

=

..

!

-1.1,1.1

.~

·A

cA

~1J

~I~ ~ ~ ~

.

_;/

,

~

_!

_~

" :> :IIU.U.U'

.~,

~ :

.

..

_-

.

1~

~

.

... !'

-

.

0

~ '

-

.-" _{f -} ~ r-. ' ,

.

>-•

t.~~~j

~.

,

;

,

l

I~

!

_•

i<

~~

,

• ,

_l,!! a;

il:.

•

,

3

;~

~

₅

₁₄

.

~ _.-;

,

•

..

.

"

.I~·

of" " ' ; :

I-;.!L

~a

D~~"~

.. : iii ;

."

;.~

;

~-~

.. ".: I

d

,

.

'I~·

Il! ii ! _~ .~

~

-,

:

_II

_:

~

_I

_~

_Ii!

~

_;

_I:

_i

•

! \~=(10"'!"~2'CU)

:;

..

Q

(8)

,

•

!

I

•

~ ~

N

"

•

0

•

~2 •

~~

"

· l!-F

-•

!

11 .

•

.~ ~ ei[

:;,.... 0

-~ <

"r

-•

•

; ~

..

- 0 •

"- r

~

~ <> co

I I I

,

o

CD

....,

r-;.

~

~L,

u

:I:

"'

,

..

«

....,

..

!

g

I

<Jl

«:

~

<Jl I 0

I-a

<Jl

u~

~

0

i

<;> jO

~

,?

~

.

\

of

j •

I

i

j

.

...

11~ 3

i

•

1

=

I

g

0:"· a

•

N