“The Novel Technique for Channel Security Using UART”

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July 7 2018, Sri Sunflower College of Engineering and Technology, Lankapalli, India.

International Journal for Modern Trends in Science and Technology (ISSN: 2455-3778), Volume 4, Special Issue 4, July 2018

167

“The Novel Technique for Channel Security Using UART”

1.Kadavakollu.Jhansi Rani

SSCET,Lankapalli

Email ID:[email protected]

2.Aluri.Revathi SSCET,Lankapalli

Email ID:[email protected] 3.Oruganti.Veera Venkata Pavan Sai Sree

SSCET,Lankapalli

Email ID:[email protected]

Abstract - In the field of communication to achieve the secured communication is the biggest challenge. The conventional techniques of transmission provide transmission efficiency but does not able to have total secured communication because of dynamic properties of channel. In this project paper after studying dynamic behavior channel we proved that this is “The Novel Technique for Channel Security”. UART (Universal Asynchronous Receiver Transmitter) is a serial communication protocol; mostly used for long-distance, high speed, low-cost data exchange between computer and peripherals. UART includes three basic modules which are the baud rate generator, receiver and transmitter. The UART implemented with VHDL language can be integrated into the FPGA (Field Programmable Gate Array) to achieve compact, stable and reliable data transmission. It is also significant for the design of SOC. In this project Paper we are concentrating on one of the most secured way of serial communication by automatic generation and detection of Baud Rate. To achieve auto bauding we adopt configuration of UART using FPGA. Due to autobauding continuous variation of baud rate by baud generator is detected by uart (receiver) but not by microcontroller (intruder). Original form of data is different than what faulty receiver collects. This system is reconfigurable and scalable and it is used to reduce the synchronization error between the subsystems with in a system.

I. I

NTRODUCTION A. Generlized Block diagram

A universal asynchronous receive/transmit (UART) is an integrated circuit which plays the most important role in serial communication. It handles the conversion between serial and parallel data. Serial communication reduces the distortion of a signal, therefore makes data transfer between two systems separated in great distance possible. Asynchronous serial communication has advantages of less transmission line, high reliability, and long transmission distance, therefore is widely used in data exchange between computer and peripherals.

Asynchronous serial communication is usually implemented by Universal Asynchronous Receiver Transmitter (UART).

Fig:1Generlize UART module B. Project prototype architecture

Fig:2 overview of prototype

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168 Transmitter:

The UART transmitting subsystem is similar to the receiving subsystem. It consists of UART transmitter, baud rate generator and interface circuit. Roles are reversed for the interface circuit, i.e., the system sets the ﬂag FF or writes the buffer interface circuit while the UART transmitter clears FF or reads the buffer.

The transmitter is essentially a shift register that shifts out data bits. Since no oversampling is involved, the frequency of the ticks are 16 times slower than that of the receiver. We can use any serial transmission unit as source like output from computer , laptops etc.

Fig:3 Transmitter state diagram Receiver

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During the UART reception, the serial data and the receiving clock are asynchronous, so it is very important to correctly determine the start bit of a frame data. The receiver module receives data from RXD pin. RXD jumps into logic 0 from logic 1 can be regarded as the beginning of a data frame.

When the UART receiver module is reset, it has been waiting the RXD level to jump. The start bit is identified by detecting RXD level changes from high to low. In order to avoid the misjudgment of the start bit caused by noise, a start bit error detect function is added in this design, which requires the received low level in RXD at least over 50% of the baud rate to be able to determine the start bit arrives.

Since the receive clock frequency is 16 times the baud rate in the design, the RXD low level lasts at least 8 receiving clock cycles is considered start bit arrives. Once the start bit been identified, from the next bit, begin to count the rising edge of the baud clock, and sample RXD when counting.

Fig:4 Receiver state diagram Baud rate generator:

It is actually a frequency divider. The baud rate frequency factor can be calculated according to a given system clock frequency (oscillator clock) and the requested baud rate. The calculated baud rate frequency factor is used as the divider factor. In this design, the frequency clock produced by the baud rate generator is not the baud rate clock, but 16 times the baud rate clock. The purpose is to precisely sample the asynchronous serial data at the receiver. Assume that the system clock is 32MHz, baud rate is 9600bps, and then the output clock frequency of baud rate generator should be 16 * 9600Hz. Therefore the frequency coefficient (M) of the baud rate generator is: M =32MHz/16*9600Hz=208. Formula for Baud Rate is Given by; Baud Rate =Clock Frequency/

(Sampling Rate) X (Divisor)(1)

Table. Various Bound rate Deviser

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169 II. EXISTING WORK

 The existing work which involves modifiable UART is not specific and rather generic, in the implementation manner. But here, in this paper, a novel approach for the implementation of architecture is proposed.

 This paper provides the comfort of adjusting all the above said parameters in a separate module, which is baud-rate generator module, without changing the top module.

III. COMPLETE ART CIRCUIT

IV. FRAME FORMAT

In Basic UART communication needs only two signal lines (RXD, TXD) to complete full-duplex data communication.

TXD is the transmit side, the output of UART; RXD is the receiver, the input of UART. UART’s basic features are There are two states in the signal line, using logic 1 (high) and logic 0 (low) to distinguish respectively. It also supports configurable baud rate generator with data length of 8 bits per frame

Fig: 6. Frame format

Figure Labels: Use 8 point Times New Roman for Figure labels. Use words rather than symbols or abbreviations when writing Figure axis labels to avoid confusing the reader. As an example, write the quantity “Magnetization,” or

“Magnetization, M,” not just “M.” If including units in the label, present them within parentheses. Do not label axes only with units. In the example, write “Magnetization (A/m)” or

“Magnetization (A ( m(1),” not just “A/m.” Do not label axes with a ratio of quantities and units. For example, write

“Temperature (K),” not “Temperature/K.”

IV. FPGA

FPGA (Field Programmable Gate Array) is using extensively and playing more and more important roles in the designing of digital circuit. Its programmable characteristics make circuit design much more flexible and shorten the time to market. Using FPGAs can also improve the system’s integration, reliability and reduce power consumptions.

FPGAs are always used to implement simple interface circuit or complex state machines to satisfy different system requirements. The programming of the FPGA is done using a logic circuit diagram or a source code using a Hardware Description Language (HDL) to specify how the chip should work. FPGAs have programmable logic components called

‚logic blocks‛, and a hierarchy or reconfigurable interconnects which facilitate the ‚wiring‛ of the blocks together. The programmable logic blocks are called configurable logic blocks and reconfigurable interconnects are called switch boxes.

FPGA architecture:

FPGA architecture depends on its vendor, but they are usually variation of that shown in the figure. The architecture comprises Configurable Logic Blocks, Configurable I/O blocks and Programmable Interconnects. It also houses a clockcircuitry to drive the clock signals to each logic block.

Additional logic resources like ALUs, Decoders and memory may be available. Static Ram and anti-fuses are the two basic types of programmable elements for an FPGA. The number of CLBs and I/Os required can easily be determined from the design but the number of routing tracks is different even within the designs employing the same amount of logic.

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170 Fig.8. Internal Logical Crcuit of FPGA

B. FPGA Design Flow

The flow for the design using FPGA outlines the whole process of device design, and guarantees that none of the steps is overlooked. Thus, it ensures that we have the best chance of getting back a working prototype that will correctly function in the final system to be designed.

 Initially We have HDL coding of design, . Basically it consist of three modules ,which design using VHDL language. Hardware baheviver of design is explained by VHDL language. • Design is compile and simulate on model sim software;that is verification of function.

 At this step we verify our design using model sim.

During synthesis ;we synthesize our design on perticuler FPGA platform. • After synthesis we generate a bitstream file for programming FPGAC.

Configration of hyper terminal to test UART module C. Configration of hyper terminal to test UART module

V. Results Baud rate generator:

For automatic baud- rate detection, a data frame is preceded by a synchronization sequence that consists of a break and a synch field. The automatic baud-rate detection mode can be used in a full-duplex communication system with some restrictions. Baud rate genrator Used to generate the baud rates for both the transmitter and receiver, Not required for any

other function including reads and writes . It has Crystal or External Clock.

Fig.10. Simmulation result of Baudrate Genrator Receiver:

During receiver simulation, after every clock event when reset is applied output is in highimpedance.when reset is low after enabling the reception data is received from receiver line.

As a start bit is 0; for eight clock cycle data received successfully then it search for stop bit. If stop bit is equal to 1then serial received data is out to store register and reset the flag of receive frame error.

Transmitter:

During transmitter simulation, when reset line is high tx. line is at high impedance .when reset is low at every rising edge of clock first eight bit data is loaded in temp.buffer.at the same time send start as zero .on txd. line, for every clock time event

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171 find 8 bit data on txd. Line after completion of eight bit data

enables the tx. Empty flag.

VI.APPLICATION

 Synchronization of Telecommunication routers in Telecommunication

 Handheld terminals • Mobile Computing in wide area of network.

 Simultaneous control of systems which provides Factory Automation

 Point-of-Sale terminals.

 Data Concentrators. • Gaming terminals.

 Portable applications. • Router control.

 Cellular data transmission and reception. In above all system’s to achieve the most secured communication we used UART.

VII. Conclusion

This paper describes the architecture of UART that support parity selection and different baud rates for serial transmission of data. Working principle of this UART has been tested using ISE simulator, which can be implemented on FPGA.

Additionally we can detect the different types of errors occurred during communication and hence correct them. This design uses VHDL as design language to achieve the modules of UART. Using Xilinx ISE software, Xilinx Spartan 3E FPGA XC3S500E chip to complete simulation and test. The results are stable and reliable. The design has great flexibility, high integration, with some reference value.

REFERANCE

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[2]. Biplab Roy “Platform-Independent Customizable UART” 2012 Third International Conference on Intelligent Systems

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[5]. Jan Henning Mueller, Mojdeh Hamzavi Nejad Moghaddam, Bastian Mohr, Sebastian Strache, Ralf Wunderlich and Stefan Heinen Chair of Integrated Analog Circuits and RF Systems RWTH Aachen University, Aachen, Germany” An Adaptable UART Based Conﬁguration and Read-out Interface for IC Prototypes” PRIME 2012, Aachen, Germany