A 2 Gbps to 12 Gbps Wide-Range CDR with Automatic Frequency Band Selector

A 2

Gbps to 12

Gbps Wide-Range CDR with

Automatic Frequency Band Selector

Abstract⎯The need for wide-band clock and data recovery (CDR) circuits is discussed. A 2Gbps to 12 Gbps continuous-rate CDR circuit employing a multi-mode voltage-control oscillator (VCO), a frequency detector, and a phase detector (FD&PD) is described. A new automatic frequency band selection (FBS) without external reference clock is proposed to select the appropriate mode and also solve the instability problem when the circuit is powering on. The multi-mode VCO and FD/PD circuits which can operate at full-rate and half-rate modes facilitate CDR with six operation modes. The proposed CDR structure has been modeled with MATLAB and the simulated results validate its feasibility.

Index Terms⎯Clock and data recovery, frequency band selection, frequency detector, phase detector.

1.

Introduction

The clock and data recovery (CDR) circuit plays an important role in wired communication systems. With the wave-length division multiplexing technique, the information can be exchanged at different bit rates in optical domain. In addition, since the power scales down as the operating frequency decreases, low speed operations can substantially reduce the power consumption of the chips. In order to meet the requirements of both high and low speed transmission, a certain type of wide-range CDR is essential to the serial link communication[1]. At last, this wide-range CDR circuit should meet the data rate requirements of various standards so that the cost of link system could be reduced[2]_{. These reasons serve as the}

Manuscript received June 20, 2011; revised August 31, 2011. This work was supported by the Hubei Natural Science Foundation of China under Grant No. 2010CDB02706 and the Fundamental Research Funds for the Central Universities under Grant No. C2009Q060.

C.-Y. Wen and W. He are with the Graduate School, Huazhong University of Science and Technology, Wuhan 430074, China (e-mail: [email protected]; [email protected]).

Z.-G. Zou, J.-M. Lei, and X.-C. Zou are with the Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan 430074, China (e-mail: [email protected]; [email protected]; and [email protected]).

Digital Object Identifier: 10.3969/j.issn.1674-862X.2012.01.012

motivation of designing a wide-band CDR circuit.

Several techniques have been used to broaden the CDR bandwidth. In [3], a dual-mode voltage-control-oscillator (VCO) with two central frequencies was used to implement the CDR circuit. However, due to the restrictions of jitter characteristics, the gain of the VCO cannot be high[4]_, which makes these CDR circuits operate at isolated rates. In [5], a VCO with more modes was adopted in order to make CDR’s range continuous.

Compared with the architecture used in [3] and [5], the proposed CDR includes not only a multi-modes VCO but also a new frequency detector and a new phase detector (FD&PD). The FD&PD can operate at full-rate and half- rate modes. With this improvement, a 2Gbps to 12Gbps continuous-rate CDR circuit without a reference clock is realized. The difficulty of the wide-band continuous-rate CDR circuit is how to choose an appropriate operating frequency band. To solve the problem, a new frequency band selector (FBS) is proposed. In addition, how to reduce the dual-modes FD&PD’s power consumption is also considered.

The paper is arranged as followed. Section 2 describes the CDR architecture. Operation principle and details of the building block are discussed in Section 3. The simulation results are shown in Section 4. Section 5 gives the conclusion of this work.

2.

CDR Architecture

Six modes of the proposed CDR are summarized in Table 1. The CDR circuit contains four-mode VCO and dual-mode FD&PD.

Fig. 1 shows the block diagram of the CDR circuit, consisting of the proposed FBS, dual-mode FD&PD, a charge pumps (CPs), a second-order low-pass filter (LPF), and a multi-mode VCO. And the FBS consists of a coarse frequency detection and a control logic.

The CDR design in this paper utilizes a novel FBS to judge an approximate scope of data rate, and create control signals to select an appropriate mode of FD&PD and VCO. The enable signal (EN) disables FBS when a mode has been selected. How to select a mode to solve the instability problem when the circuit is powering on must be carefully

onsidered in this circuit. c

FD/PD Full-rate Full-rate Half-rate Half-rate Half-rate Half-rate

Fig. 1. Architecture of the CDR.

Fig. 2. Proposed frequency band selector.

Fig. 3. Coarse frequency detector.

3. Building Blocks of the CDR

3.1 F

n Fig. 2. In order to select an

he presence of rising edge during ΔT

as shown in Fig. 3. N can be expressed as

requency Band Selector

The proposed FBS is shown i

appropriate mode when the circuit is powering on, FBS should have the ability of detecting frequency. But a conventional rotational frequency detector has a limited acquisition range of about ±50%, and is susceptible to harmonic locking[6]_{, so it can not satisfy this application.} This paper presents a new coarse frequency detector (CFD) to solve the problem.

The CFD counts t

N≈ Δkf T (1) where f is data rate and k is tr

ore digi

ansition rate. f can be concluded from (1) when the values of N, k, and ΔT are already known. When data type is non-return-to-zero (NRZ) pseudo-random-binary-sequence (PRBS) or NRZ clock pattern, k is 0.25 or 0.5, respectively[7]_{. The delay cell} creates ΔT, the six D flip-flops (DFFs) sample the output of CFD after ΔT, obtaining the control signals of FD&PD and VCO. Meanwhile, OR_1 generates EN to disable FBS.

If the ΔT is too long, the counter would need m ts and consume more power; but if the ΔT is too short, the counter could not satisfy the application of wideband frequency detection. Based on the frame structure of IEEE 802.3, which has 7 bytes clock pattern in the front, k is 0.5. We can obtain ΔT=2ns from (1). Supposing N≈ f , as a result, a four bit binary counter (B3B2B1B0) ld be enough.

T

wou e instable period when the circuit is powering on as

wn in Fig. 5 (a). Signals from FBS

r

when VCO’s frequency is within PD

1 is th

shown in Fig. 4. Unfortunately, T1 is uncertain, so if CFD works immediately when the circuit is powering on, it would obtain a wrong result, as shown in Fig. 4 (a) and (b). A NOR_1 is added into the circuit to solve this problem, which makes sure that CFD starts to work when B3B2B1B0=0000 and T1 no longer affects the frequency detection result, as shown in Fig. 4 (c).

3.2 Frequency Detector

The proposed FD is sho

control S1 and S2. When S1 is on and S2 is off, FD is a rotary frequency detector in [3]; in contrary FD works as half-rate mode like [8]. We can conclude from Table 1 that Mode 3 and Mode 1 have the maximum 20% offset between data rate and VCO center-frequency compared with other modes. According to [7] and [8], the FD can satisfy this offset.

3.3 Phase Detecto

PD starts to work

’s acquisition band. The proposed dual-mode PD is shown in Fig. 5 (b). When S1 is on and S2 is off, PD works in full-rate mode and ERROR_1 and REF_1 are effective. The two latches in dotted line box form master-slave DFF just like Hogge full-rate PD dose. In contrary, PD works at half-rate mode. Compared with the method in [4], the proposed PD consumes less power and saves area.

WEN et al.: A 2Gbps to 12Gbps Wide-Range CDR with Automatic Frequency Band Selector

(a)

(b)

(c)

Fig. 4. T1 instable period: (a) wrong result when T1 is long, (b) wrong result when T1 is short, and (c) CFD starts to work after T1.

(a)

(b)

Fig. 5. Dual-modes: (a) dual-mode FD and (b) dual-mode PD.

tion Results

Fig. 6 s s d CDR in

MATLAB. A n ock pattern

hea

input data rate from 2Gbps to 12Gbps. Fig. 7 shows the . VCO’s frequency is equal to data rate in

Fig. 6. Proposed CDR circuit.

4.

Simula

how the model of the propose ll i put datas have a 7-byte cl

der and change to PRBS to simulate the frame structure of IEEE 802.3.

To verify the acquisition ability of the CDR, we set the

VCO’s frequency

Fig. 7 (a) and is as half times as data rate in Fig. 7 (b), because the FD/PD works at full-rate mode at the former and at half-rate at the later. And the acquisition time is less than 12μs.

)

)

Fig. 7. VCO’s output frequency n: (a) when data

rates are 2Gbps, 3Gbps, and 4Gbps, respectively and (b) when

data rates are 6Gbps, 8Gbps and 12Gbps, respectively.

Fig. 8. VCO’s frequency: (a) when the phase step responds (b) when the frequency step responds.

output data of the proposed CDR: (a) Din and (b) out.

Table 2: Performance comparisons

ase abi input

h has at 1 8 ( e r

that VCO’s frequency has a tremble at 15μs and goes back to stead

esents a design procedure of wideband CDR, and presents a continuous-rate CDR with the

procedure. With t ode FD&PD,

the receiva

orks Acquisition _time Data rate _(Gbps) Architecture Ext. Ref. clock )

Fig. 7. VCO’s output frequency n: (a) when data

rates are 2Gbps, 3Gbps, and 4 bps, respectively and (b) when

data rates are 6Gbps, 8Gbps and 12Gbps, respectively.

Fig. 8. VCO’s frequency: (a) w en the phase step responds (b) when the frequency step responds

output data of the proposed CDR: (a) Din and (b) out.

Table 2: Performance comparisons

ase abi input

h has at 1 8 ( e r

that VCO’s frequency has a tremble at 15μs and goes back to stead

esents a design procedure of wideband CDR, and presents a continuous-rate CDR with the

procedure. With t ode FD&PD,

the receiva

orks Acquisition _time Data rate _(Gbps) Architecture Ext. Ref. clock (a (b (b when acquisitio when acquisitio , 10 Gbps, , 10 Gbps,

Fig. 9. Input and Fig. 9. Input and

D D

To verify C

To verify CDR’s phDR’s ph lockinglocking lity, the lity, the datadata as 0.5-UI p

as 0.5-UI p e step e step 55μμs. Fig. s. Fig. a) shows tha) shows th esult esult y after that.

Fig. 8 (b) shows the circuit’s frequency tracking ability. The data rate changes from 6Gbps to 5Gbps at 10μs, as a result, the VCO’s frequency changes from 3GHz to 2.5 GHz.

y after that.

Fig. 8 (b) shows the circuit’s frequency tracking ability. The data rate changes from 6

At last, Fig. 9 shows the recovered data output from the circuit. We can see that output data lags behead input data by 1-UI. The performance comparisons of this work are listed in Tab

At last, Fig. 9 shows the recovered data output from the circuit. We can see that output data lags behead input data by 1-UI. The performance comparisons of this work are listed in Table 2.

5 Conclusions

5 Conclusions

he proposed FBS and dual-m he proposed FBS and dual-m

ble data rate of CDR is from 2 Gbps to 12 Gbps. We can broaden the acquisition band through combining multi-mode VCO and multi-mode FD&PD.

ble data rate of CDR is from 2 Gbps to 12 Gbps. We can broaden the acquisition band through combining multi-mode VCO and multi-mode FD&PD.

W Required W Required G h . Gbps to 5Gbps at 10μs, as a result, the VCO’s frequency changes from 3GHz to 2.5 GHz.

This work <12μs 2–12 Full-rate/ _Half-rate No ASSCC’10[1] < 0 < 0.15/0.6/ 0 NA 0.250–5 quarter-rate Yes ISSCC’11[2] _{0.25ms .5–2.5 Half-rate No} ISSCC’06[9] _25ms 1.2/2.5 Full-rate No ISSCC’05[10] _{<1ms .012.5–2.7 Full-rate No} 0 2 4 8 10 12 Tim 6 e (μs) 2.5 2.0 1.5 Fr equency ( 0 2 4 6 8 10 12 Ti em (μs) 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 Fr equency ( GHz) 2 4 6 8 12 14 16 18 Tim (μs) ) 10 e (a 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 Fr equency ( GHz) 0 5 10 15 Tim (μs) ) e (b 3.0 2.5 2.0 1.5 1.0 Fr equency ( GHz) Ti (μs) ) me (a 1.0 0.5 0 ltag e (V) V o 1.250 1.252 1.254 1.256 1.258 1.260 Time (μs) (b)

WEN et al.: A 2Gbps to 12Gbps Wide-Range CDR with Automatic Frequency Band Selector

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Chao-Ye Wen was born in Guangxi Province,

China, in 1987. He received the B.E. degree in electronic science & technology from Huazhong

the M.S. degree in electrical & electronic engineering from HUST

.S. degree in physics from Wuhan University, Wuhan, in 2009. He is

n 1975. He received the M.S. degree and the Ph.D. degree in micro-electronics and

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University of Science and Technology (HUST), Wuhan, in 2009. He is currently pursuing the M.S. degree with the Department of Electronic Science & Technology, HUST. His research interests include analog IC design and mixed-signal IC design.

Zhi-Ge Zouwas born in Hubei Province, China,

in 1975. He received

in 2003. He received the Ph.D. degree in micro-electronics and solid state electronics from HUST in 2008. He is currently an associate professor with the Department of Electronic Science & Technology, HUST. His research interests include analog IC design and mixed-signal IC design.

Wei Hewas born in Hubei Province, China, in

1986. He received the B

currently pursuing the M.S. degree with the Department of Electronic Science & Technology, HUST. His research interests include analog IC design and mixed-signal IC design.

Jian-Ming Lei was born in Hunan Province,

China, i

solid-state electronics from HUST in 2001 and 2004, respectively. Now he is an associate professor with the Department of Electronic Science and Technology, HUST. His research interests include mix-signal IC design, CMOS-RF IC design, semiconductor, and CMOS-MEMS technology, especially in ultra-high-speed communication circuit.

Xue-Chen Zou received the M.S. degree and

the Ph.D. degree in micro-electronics 1995, respectively. He did postdoctoral research with City University of Hong Kong from 1996 to 1998. Now he is the Chairman of the Department of Electronic Science and Technology, HUST. His research interests include VLSI, microelectronic device, and Internet of things.