2T XOR Based Content Addressable
Memory
A.Lavanya
Assistant Professor, Department of Electronics and Communication Engineering, Karpaga Vinayaga College of Engineering and Technology, Chengalpattu, Tamilnadu,India
P.Poorani
Assistant Professor, Department of Electronics and Communication Engineering, Karpaga Vinayaga College of Engineering and Technology, Chengalpattu, Tamilnadu,India
J.P.Shri Tharanyaa
Assistant Professor (Sr.Grade), Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam.
Abstract— Content-addressable memories (CAMs) are hardware search engines that are much faster than
algorithmic approaches for search-intensive applications. CAM is capable of searching its entire contents in a single clock cycle. It is a type of storage device and it addressable by its own contents. Content addressable memory used in various applications like lookup tables, database and ATM that require high-speed searches due to its ability to improve performance by using parallel comparison to reduce search time. It use the parallel comparison result in fast search time, it significantly increases power consumption. Parameter Extractor is the part of the CAM, which consumes more power. CAM follows the precomputation method in this the extractor extracts the parameter form the input data and compare the parameter with the parameter stored in parameter memory. Generally, Two methods are used to design the parameter extractor in CAM architecture; once count approach and Block XOR approach. These methods had designed with traditional 14T XOR module which consumes more power and area and 4T XOR module which consumes less power and high speed. Novel 2T XOR method is introduced to replace 4T XOR module in order to achieve Higher speed, low power consumption, low space. In this parameter extractor, parameter memory and data memory are designed with P-MOS and N-MOS transistor using Tanner T-spice CMOS technology. The parameter extractor with the proposed 2T XOR method on a CAM architecture has more advantage than the traditional 14T XOR and 4T XOR architecture in terms of power consumption, delay and area.
Keywords— CAM, Block XOR, 4T XOR, 2T XOR, Power Consumption.
1. INTRODUCTION
The trend towards low power design depends on two forces, The demand for portable equipment and limitations of higher performance VLSI based systems. For Portable equipment design major goal is low power consumption. For Higher performance VLSI based systems the high speed and high speed integration is main consideration but system will produce a dramatic increase in heat dissipation. Portable equipment encompass high-throughput.
The practical limitation in the CMOS circuits is as follows
1. When capacitive loads are imposed on the power supply current I, it is necessary to obtain a given bandwidth which is inversely proportional to the transconductance to current ratio gm/I of the active device. The small value of gm/I inherent to MOS transistors operated in strong inversion may therefore cause an increase in power consumption.
2. The presence of additional sources of noise implies an increase in power consumption. These include l/f noise in the devices and noise coming from the power supply or generated on chip by other blocks of the circuit.
3. The need for precision usually leads to the use of larger dimensions for active and passive components, with a resulting increase in parasitic capacitors and power.
Interest in and evolution of low-voltage, low-power circuits have grown rapidly from applications on watches and medical electronics such as pacemakers, hearing aids, blood flow meters to a host of other applications. This increased interest is mainly due to commercial implications of portable equipment, power reduction on
non-battery-powered systems and consumer electronics. Some of these examples are the laptop/notebook computers as well as workstations, PCs, electronic organizers, language translators, electronic dictionaries, implantable devices, portable radios and TV sets.
1.1 CAM
Content-addressable memory (CAM) is a special type of computer memory used in certain very-high-speed searching applications. It is also known as associative memory or associative storage and compares input search data (tag) against a table of stored data, and returns the address of matching data or in the case of associative memory the exact matching data CAM provides an efficiently fast data-search function. Usually in data searching operation CAM uses the parallel comparison structure method for data comparison. Due to Less power consumption and high speed implementation always the parallel process comparison is best method for higher achievement.
CAM has a single clock cycle throughput making them faster than other hardware- and software-based search systems. CAM can be used in a wide variety of applications requiring high search speeds. It is frequently used in applications, such as lookup tables, databases, associative computing, and networking. The above Fig. 1 Shows the CAM architecture.in this CAM has a two parts: Parameter Extractor and Parameter Memory. The parameter extractor is highlighted in a figure 1.
Figure. 1 CAM Architecture
1.1.1 Parameter Extractor
Parameter extractor is a part of CAM architecture which can be work in two ways. During data write operation, input data extracted using parameter extractor and it stores the input data in a Data memory and its parameter in the parameter memory. During Data searching operation, the large amount of comparison process involved in order to reduce that comparison process, it is done by two ways.
1.1.2 Parameter Memory
In the first way, the parameter extractor extracts a parameter from the given input data, it is compared to parameters stored in the parameter memory. If any mismatch is found in the first part, the input data related to those stored parameters have to be compared in the second part.It the first part it access the entire parameter memory, the parameter memory is smaller than the content addressable memory. Comparisons made in the first part will filter the unmatched data, then second part will need to compare the data that match with the first part. In recent Research, Reducing the power consumption without compromising the area and speed is the main thread in large capacity CAM. Tanner EDA tool is used to design a parameter memory, Data memory and Extractor to achieve the higher performance with low power consumption.
2. EXISTING SYSTEM
For speedy search applications, a content-addressable memory (CAM) is special type of computer memory is used.in this once the parameter match with the input data it returns the address as the output.it requires more number of comparisons so, CAM requires high power consumption.
CAM mainly used in a high-end networking devices which requires the high speed operation and low power consumption to withstand for longer time.in a CAM the cache methods (filter and location) techniques can effectively reduce the power dissipation. CAM generally implemented using two way ;Once count approach and block XOR method.
2.1.1 Once Count Approach
CAM architecture adopts ones count function to perform the parameter extraction, with an n-bit data length; there are n+1 kinds of one’s count (from 0 ones count to n ones count). Furthermore, it is necessary to add an extra kind of one’s count to indicate the availability of stored data. Based on this parameter extraction function, the minimal bit length of the parameter is equal to [log (n+2)]. The required bit length of the parameter is log (n+2).
In the PB-CAM architecture design, with an m words by n bits CAM size, the average number of data comparisons in the second comparison process is m/(n+1) , since there are n+1 kinds of one’s count, and only one kind of one’s count (matches with the ones count of the input data) is unidentified in the parameter comparison process.
Figure. 2 Shows the 14 bit parameter extractor based on the ones-count approach is implemented with full adders which consumes more power compared to Block Xor approach.
Figure 2 Ones count function
2.1.2 Architecture of Block-Xor
One of the disadvantages in this circuit is it using full adder it consumes more power consumption and requires the large space. Block-XOR module is designed to overcome the drawbacks of one’s count approach.For a 14-bit input data[1], if we can issue the input data homogeneously over the parameters, then the number of input
data related to each parameter would be 2^14/15=1093, and the maximum number of required comparison operations would be 2^14/15=1093 for each case in the second part of the comparison process. Compared with the ones-count approach, this approach can reduce comparison operations by a minimum of 909 and a maximum of 2339 (i.e., for parameter value is from 5 to 9) for 82% of the cases. Block-XOR, In this approach, the input data bit is first partition into several blocks, from which an output bit is computed using XOR logic operation for each of these blocks. The output bits are then combined to become the input parameter for the second part of the comparison process.
The concept of this approach does not provide a valid bit for checking whether the data is valid; hence it cannot be applied to the PB-CAM directly. For this reason, Figure. 3 shows the modified the architectures shown in the lower part to provide a valid bit and to guarantee the uniform distribution property of the Block-XOR approach and a multiplexer is added to select the correct parameter.
Figure.3 Concept of n-bit Block-XOR block diagram 3 PROPOSED SYSTEM
3.1 XOR
Xor gate is the basic block in the both once count and block xor module so the 4T xor module was designed to show the variation in the power, speed and area.
Basic cell in digital computing systems is the 1-bit XOR which has two 1-bit inputs (A, B) and one 1-bit output (Y). The relations between the inputs and the outputs are expressed as in equation (1) and fig 4.
y=ab’+a’b (1) 3.2 Conventional 14T XOR Design
XOR module as shown in Figure. 5. is the conventional type it consists of 14 CMOS transistors and requires the input supply voltage between 3 to 5.
Figure. 5 14T XOR Design
This Design is implemented by a TSPICE-20µm CMOS technology. This conventional method consumes more power compared to proposed XOR technology.
3.3 4T XOR Module
Conventional method consumes more power in order to reduce that 4T XOR Design was developed which consumes less power and high performance compared to conventional design. In this 4T XOR module does not require any input. For supply voltage vdd the input is given as supply voltage. This xor module consists of 4
transistors. Figure. 6 is 4T XOR design, this circuit power consumption is very less compared to the basic 14T XOR module.
Figure. 6 4T XOR Design 3.4 Proposed 2T XOR and Full Adder Design
In a proposed 2T XOR module it does not have any input, only two transistors required to implement the 2T XOR module. It does not require any operating voltage vdd. The input A and B can act as vdd. based on 2T XOR module PB CAM was designed to achieve a higher performance. The Figure 7. Shows the proposed 2T XOR Module method.
Figure. 7 Proposed 2T XOR Design
The Proposed 2T XOR module has no input so that amount of power consumption was very low. Figure. 8 shows that full adder with mux which does not require and gate to perform the product operation.
Figure. 8 Full Adder without AND Gate
2T XOR module and Full adder without AND gate transistor level, Power consumption and delay was reduced compared to other circuits.
3.5. Proposed Parameter Extractor
Parameter extractor designed using once count Approach and block Xor methods. In a proposed system the parameter extractor designed with 14T ,4T,2T methods and comparisons was tabulated in section 4.1.
3.5.1. Once Count Approach with 2T XOR
In this module, full adder uses a two 2T XOR and one MUX module. It consists of an only 6 transistor. it consumes a very low power and low space so it can perform a high speed operation compared to basic parameter Extractor implantation with 14T and 4T modules. The Figure. 9 shows the modified parameter extractor with once count approach based on 2T XOR module. Full adder design converted into a block.
Figure. 9 Parameter Extractor with once count approach based on 2T Xor
3.5.2 Proposed 2T Block-XOR module
This XOR module consists of 2 CMOS transistors, Block-XOR circuit given in Figure.10 uses 6 XOR and 4 input AND gat. In this the multiplexer is used for selecting an correct parameter. The buffer in a circuit used to produce a delay in this Design.
Figure. 10 Proposed 2T Block-XOR module
3.6 Proposed Parameter Memory
During data write operation Extractor extracts the parameter from the input and store it into a Parameter memory. During data read operation it compares the given input data with a stored data in memory. The proposed Parameter memory is shown in Figure. 11 which consists of Static RAM, D Flip Flop, and gate to store the Parameter.
Figure. 11 Parameter Memory
3.7. Proposed Data Memory
In data read and write operation generally data will reside in a data memory. The static random access memory can retain its stored information as long as power is On. Figure12.shows the structure of storage cell for storing one bit information. The core of cell is formed by two CMOS inverters, where the output potential of each invertor is given to input to one another. Conventional SRAM core cell that stores data using positive feedback in back-to-back inverter. The two access transistors connect the bit lines, b and b bar to the storage nodes under control of word line w; Data can be read from the cell or written into the cell through the bit lines.This different cell is used as storage for building CAM cells.
Figure. 12.One bit Data Memory
The circuit shown above is used for storing only one bit this is called as a 1 bit cell, for storing n number of bits more than one bit number of cells is used. Figure. 13 shows an n bit RAM cells [6]..
Figure. 13.Data Memory 4 RESULTS AND DISCUSSION
4.1 Simulation Result for 2T XOR Module
The 2T XOR design was developed using Tanner EDA tool the results are shown in Figure. 14 the input is a and b and the output y that shows the clear result for 2T XOR module. In 2T Xor module
Figure. 14 Simulation output for 4T XOR Module
4.2 Comparison with Different XOR Modules
In CAM architecture the main parts are Parameter extractor,Paarameter memory and data memory. The entire CAM architecture designed with tanner Eda tool and result was compared. Especially the Parameter Extractor was Designed using 14T,4T,2T Xor modules and result was compared with table 1.
Table- 1 14T ,4T and 2T Xor Comparisions Module Power (watts) Delay Time Transistor Levels 14T Xor 2.578e-002 4.95 748 4T Xor 5.167e-008 0.31 82 2T Xor 1.118e-008 0.11 42
The parameters Power, delay and transistor levels compared with various 14T, 4T, 2T Xor moduls result clearly says that 2T Xor modules consumes very less power and number of transistor was very less and produce high speed operation. By using tanner Eda tool the Parameter memory was designed with 302 transistors and Data memory designed with 96 transistors. Table -2 shows The entire CAM architecture Power consumption, delay, transistor level for 4T XOR module.
Table -2 : CAM design with 4T Xor Module
Module Power (watts) Delay Time Transistor Levels Parameter Extractor 5.167e-008 0.31 82 Parameter Memory 9.354e-007 10.08 302 Data Memory 2.118e-002 1.02 96
Total CAM 4.57e-004 13.73 480
Table-3 shows that result for total CAM architecture based on 2T Xor module. Table -3 : CAM design with 2T Xor module approximately
Module Power (watts) Delay Time Transistor Levels Parameter Extractor 1.118e -008 0.11 42 Parameter Memory 9.354e-007 10.08 302
Data Memory 2.118e-002 1.02 96
Total CAM 4.57e-004 13.73 440
The table 2 and 3 shows the comparison of CAM architecture between CMOS 4T block XOR module and 2T block XOR module. From this it is clear that 2T Block XOR module is higher performance design. It was suitable for the parameter extractor design compared to 14T and 4T XOR modules.
5 CONCLUSION
CAM is a content addressable memory it is addressed by its own content. It is mainly used in high end networking devices which requires high speed operation. Parameter extractor plays a very important role in CAM Architecture which consumes high power, it is designed by one’s count approach and Block -XOR approach with 14T,4T and 2T XOR modules. By comparing the different methods of implementation the 2T XOR logic consumes very low power, less area and provide high speed operation. Comparing the once count approach and block XOR approach designed with 2T XOR module it is found that Block XOR module designed with 2T XOR module is considered as a Optimized method for CAM architecture. By comparing the transistor levels, the CAM architecture contains only 440 CMOS logic transistors based on 2T XOR which is best optimized method for CAM architecture.
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