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Turbo encoder
Interleaver
MATLAB Code
HOST PC
FPGA
(For storing information
to be transmitted and
sent out to the RF
frontend)
I_ant1 [7:0]
Q_ant1 [7:0]
I_ant2 [7:0]
Q_ant2 [7:0]
I_ant3 [7:0]
Q_ant3 [7:0]
Dual Port DAC
Dual Port DAC
Dual Port DAC
MAX2721
MAX2721
MAX2721
M_ant1_I(t)
M_ant1_Q(t)
M_ant2_I(t)
M_ant2_Q(t)
M_ant3_I(t)
M_ant3_Q(t)
MAX2750
(VCO)
De-interleaver
ML-APP
Detection
MATLAB Code
HOST PC
FPGA
(Forming the trace data
that will be processed
offline)
I_bar_ant1 [7:0]
Q_bar_ant1 [7:0]
I_bar_ant2 [7:0]
Q_bar_ant2 [7:0]
I_bar_ant3 [7:0]
Q_bar_ant3 [7:0]
Dual Port ADC
Dual Port ADC
Dual Port ADC
MAX2701
MAX2701
MAX2701
M_bar_ant1_I(t)
M_bar_ant1_Q(t)
M_bar_ant2_I(t)
M_bar_ant2_Q(t)
M_bar_ant3_I(t)
M_bar_ant3_Q(t)
MAX2750
(VCO)
Turbo Decoder
Tx
Antenna
Rx
Antenna
SISO Processor1
SISO Processor2
interleaver
interleaver
De-interleaver
Parity bit from encoder1
Parity bit from encoder1
Systematic input
Hard
Decision
Estimated
Information
Bit
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“Upper” Encoder
interleaver
Data input
Parallel to
Serial
Converter
“Lower” Enoder
Interleaved Input
uninterleaved
parity
interleaved parity
Systematic Output
Output
4?#:L 5 =5&&
&""" )"" #
( ) , % , +
- # ") ( (!
$""+ * " (# ,
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") ,")+ -(
1 - )# 0" ",#
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Interleaver
D
D
D
X
ik
X’
ik
Z’
ik
Z
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X
ik
X
t1k
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t2k
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(("+ $3 , # (
+ . # (
( (L
. N7 $
N E N
E+ ( /
N ¼
E + (
. N $ $ +
N
E . :
N ¼
E + :
. N$ +! $ + ,
N
E . 6
N ¼
E + 6
.! /* &
3 ,("( (3
"() "(" #
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. + )" , 7 :
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SISO
decoder
SISO
decoder
interl
eaver
De-interl
eaver
R(X
k
)
R(Z
k
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R(X’
k
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V
1
(X
k
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L
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k
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2
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k
)
V
2
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k
)
L
2
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k
)
L
2
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k
)
Hard
Decision
w(X
k
)
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¼
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¼
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RF
BAND PASS
FILTER
LOCAL
OSCILLATOR
RF
IF
BAND PASS
FILTER
LOCAL
OSCILLATOR
IF
90
o
BASEBAND
LOW PASS
FILTER
BASEBAND
LOW PASS
FILTER
I
(in-phase
component)
Q
(quadrature
component)
Low Noise
Amplifier
Interference
Rejection
Image
Reject
Filter
4@#:L + )
1
"((0 )1 +
# + ) ,
/@#:L
4 " " ",3 ("/ $*
/" ( 2 #
(0 , 4 1 + , ) "
( 1 + $ 4*# + ( 2 /"
2 ( " , )
1 +#
1 & 2
" "" J3 4 (+ , + 3
! , 1 +#
, / @#6# - ( + +
) "+ ( 4 )3
RF
BAND PASS
FILTER
LOCAL
OSCILLATOR
RF
90
o
BASEBAND
LOW PASS
FILTER
BASEBAND
LOW PASS
FILTER
I
(in-phase
component)
Q
(quadrature
component)
Low Noise
Amplifier
4@#6L 3 ) )
(" " , 4 (
-( ")" + )"
, ,#
,"" 0 )(4
# ())
( (1 (2 /"
() ( (0 4 ,+
,#
1 & 2
) (2)) + )
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+( " ( (#
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%-. *'
Data Acquisition Module
Data_value<47:0>
Clk
read_rs232
reset
start
done
status
uart_xmit_dataH
xmit_doneH
4 B#:L ")"" . 1 ("
-3"( ("(
( ((+ , ," ,.
, # (
(" , /B#:#
89 ( A ## &3:@7 0 "# (
4&5 ".A6#
4&5 ".# $, :77! "0" "" +
"" . 4&5*#
" ( " ((+ 36=6#
, 4&5 "
"M,#
+( #
" ( ")" ("
A #
" (" 36=6# 3
"#
)"," (" ( ##
((+ /"" + ( A#
" + % " . , 1 ("# 3
36=6 #
(" (" 0" 89
)+ " . + " , ((+ 4&5#
((+ "" & "
(( "" 36=6 , + ( 01 2
+ , ,* # (" #
" . 1" . , / B#6#
("+ M ) " ,
-" .# ". " . "#
3 0
" . " ( ((+# A
, " 4&5 " .# 4
" . , / B#=#
, + " "" " . ,"" A
# )+ " . "" ( A " .
( " ;@ ((+ ,# ((+ , ,"" ,
. = " =6 ((+ , "#
"+ 88" " . , "+ 86 (#
, " .#
:# +( ( A /"" ((+#
( ,"" , / B#8#
6# ((+/"" ( ",., %
, " . , , # , , (
((+ )+ ( '. " ) + " .# /
( ((+ " 1 0" ! " ) . .
- " #
3
" . . , % (
" . 1("+) '. " (3
" .,,;@, ) 3 2 "
%,9 +""+# ;@
" :6 , 9 %#
3 /
% ( ( "(
36=6# 36=6 4&5 /, ",
/ B#@# , (/ + F66G#
03 & )"( ) <3; ("
6=6 # "! C=66=) )
"# " <3;
) # % 36=6
# - " . % , / B#B#
( . " " +( " . H"I +
!" #$ N%$&$'()* (+:@*
, '()* (+ ( ## O
O+ $"*O $*# '()* (+ (/0
+ " 36=6 (( #
( " (( , / B#9
" ("(
9 (#
4 ( , / B#;#
3 2 % C 36=6)
3!
% "" ( # 6 #
:#/ "L
:#:* #
:#6* " /# <
+#
:#=* /#
:#8* < 3 ) <+ ) , <+#
:#?* 4 4 " /#
6# ( L
( 36=6 "" (# 3(
"+ "" < " ,
# ':("++(#
/" +
TRACE FORMATION
BLOCK
data_value[47:0]
read_rs232
Clk
reset
start
data_value[47:0]
read_rs232
Clk
start
reset
INTERFACE UART
TRACE FORMATION
data_out[7:0]
data_out_en
done
status
data_in[7:0]
data_out_en
done
status
Clk
deassert_xmitH
reset
Xmit_doneH
data_out[7:0]
read_check
xmitH
UART CORE
Clk
reset
Xmit_dataH[7:0]
uart_rec_dataH
xmitH
deassert_xmitH
uart_xmit_dataH
Xmit_doneH
read_check
read_check
done
status
uart_xmit_dataH
Xmit_doneH
rec_dataH[7:0]
rec_ready]
S0
reset
S1
Start == 0
Start == 1 / enable read_lower (to form lower 48 bits of memory word)
S2
Stall cycle to read interface
S3
Enable increment of destination address in
memory
Enable formation of higher 48 bits of memory
word
S4
Enable write to block of
SelectRAM memory [3 blocks
of SelectRAM written together]
S5
Memory full
read_check == 0 || read_rs232 == 0
Memory not full &&
SelectRAM blk not full /
(enable lower_read)
Memory not full &&
SelectRAM blk full /
(enable lower_read and
enable new SelectRAM Blk)
S6
Increment memory address (makes it 00)
S7
Enable read from memory
Stall cycle to read from memory
S8
Memory not empty && read_check == 0
Memory not empty && read_check == 1
S9
Memory full
FPGA
clock
I/O
clock
start
Data
seen at
interface
Form
lower
48
bits of
96 bit
mem
ory
word
Form
upper
48
bits of
96 bit
mem
ory
word
stall
memory
Write to
Form lower
48 bits of
96 bit
memory
word for
next
address
one 96 bit
write to
memory
S0
reset
S1
Status ! = 0
Status == 0 / (read_check = 1)
S2
S3
Data_out_en = 1/
(reset_count_12 = 1)
S4
S5
Deassert_xmitH != 1 /(dec_count_12 = 1)
/(read_96_en = 1 ) ; to read incoming memory word
Done!= 0 && count_12 !=0 / (xmitH = 1)
S6
xmit_doneH !=1
S7
done == 1
Data_out_en !=1/ (read_check = 1)
Stall cycle for data to be read
from memory in Trace Formation
Block
Stall cycle for data to be read into
register in interface
Deassert_xmitH != 1 /(xmitH = 1)
xmit_doneH !=1
Done!= 0 && count_12 ==0 /
(read_check = 1)
4 B#?L 4 , ( " .
BAUDRATE
GENERATOR
RECEIVE MODULE
uart_rec_dataH
Clk
reset
Sys_rst
Clk
reset
done
uart_xmit_dataH
Xmit_doneH
Sys_Clk
uart_rec_dataH
reset
Clk
rec_dataH[7:0]
rec_ready
TRANSMIT MODULE
xmitH
reset
Clk
Uart_xmit_dataH
Xmit_doneH
xmit_dataH[7:0]
xmit_dataH[7:0]
xmitH
deassert_xmitH
Rec_readyH
rec_dataH[7:0]
4B#BL <" . ")" ( %
Stop
Start
D0
D1
D2
D3
D4
D5
D6
D7
Time
Data Byte
Logic
0
Logic
1
S0
reset
S1
Status == 0 / (read_check = 1)
S2
S3
Data_out_en = 1/
(reset_count_12 = 1)
S4
S5
Deassert_xmitH != 1 /(dec_count_12 = 1)
/(read_96_en = 1 ) ; to read incoming memory word
Done != 0 && count_12 !=0 / (xmitH = 1)
S6
xmit_doneH !=1
S7
done == 1
Data_out_en !=1/ (read_check = 1)
Stall cycle for data to be read
from memory in Trace Formation
Block
Stall cycle for data to be read into
register in interface
Deassert_xmitH != 1 /(xmitH = 1)
xmit_doneH !=1
Done!= 0 && count_12 ==0 /
(read_check = 1)
* '
,"" ) 1 . )), ( ( (
" ) (" #
- (".
-(" " .,"+
() , (" , (
) 36=6#
4 0
)") )" , (((+ :77!#
, , (
C6&B F?G# , (" "
( ( " (" , ,
- # , (" +
" , # - ,
-", , "
(" "., ("
( .# " (" ) ,
+# 4" A ", +",
#
4 2
(" 1 (" (
( ,+ ) # /""
((+ 0 ""+)36=6#
, #
( , /" H-I , 0 (
#
4
, " )#
"(/"+"" .)+C C
&2 )L
0(( 1 + L :=6#B ! $)) (*
( " 4&5L @69 ?887 $::R*
4( ) , +( "" "! 9;R
" "" # ( +(
- , (// "
49#:L <)A7 3&& :@D=0=+(
(, +( 808 /
( "(" ("
M ",., ( ("
Æ )(# M (
" " - + " ## ""
1 " ( # "
" Æ ("0 )"# " ",
"( ( "( )(""
+("# % ( +" , , 8 (0 ,
( # 4)8"
(+ Æ (")! ()
:# ("( 45 <
# "
(" ) ! ( , ) # ) "
, "" :# + :A8 :@3D#
(" , < ) , / 9#: ,
)- (# '"("
=0= / 808# " 83D ""
# 0" ()
( )# ) =
< ()() ) = 0 = < :7
#
- "
4 9#6L < ) A7 8 " . ! :7777E (
,
" ( ( <&
("'5 "( /" )# ("
,"""! " )", ""+
"# (" F==G# " (
(" < ) A7 , / 9#6 )/
( " F=:G# -
2/ ( .#
"( (" (""," ("
( 0 ," , ) )+ #
M ) ("+# (
:7777 (" ), .
1(""(",". 6,.#
-' * 1
0 "
")), 3
(""+(# " 3
! +( ,"" ! 3"!
3" # +( " .3
, 1 4&5 ," "" "
<# ". / +(L
, 86 88:@ "" . "
4&5 (# )@99("# ("
89"((" :8==@("#
)(" 8 , ) =?89 (" " ( ("#
, ?77 (" " ( ,
" = (" (# '
$<*("(# ,"".(" ""
" 0("+=@777 (# " (
( < :7 # ""+ " (
) < ) :7 F:8 :7G
" )Æ ( ! (
#
0 & 1
( ( ( < ("(
+ ! " (# ' ,"" ()
((!43
,")"( 976#::# "3
" " ". #
) "( ( ( + - )( 3
( " ") + 3
# " ( (2 , " .
F:G <"" "(/0 ,"(L <""
" ; ( :;;9#
#
F6G #
F=G :#95! 6#?5! , ) )# )""
#
F8G & " "" &# =5&& # #
5: :@$77*:6:;#
F?G 03 & $&8A&B* )"( < K # )""
( ! " #
##$# ##
F@G ## 3) )# 1
6( - *( # :;;?#
FBG # 2 # < . # < 5# 2. # 5) # # 2
#"##(!2#"#! ##'".
# # '". '".+# &+ 0 < )
5 '"+(# 1 6( *
F9G # # " 4 ", # Æ "(
"L 5( " 0( #
1 ) ) 677=#
F;G " 5
. # 4"0" ""808 #
F:7G . < C '# " &
(( 3 &(# )"" ( % $ "
&' %( #
F::G #<# 3 L %"(("S
*( 6( #677:#
F:6G # <# '" +(L & " &" &"(
& # *7 8!9.' 2 . + 6776#
F:=G # # 5 # # ) 5# # ',# :;#6 (A 8 0 8
<A , # *7&1*
677=#
F:8G ) 5 / & # ( +(
# 4( + & L )), 3(
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677=#
F:?G #5""#<##< . ## &+
808<3)3%,".# ):- '!, '* -
; *( 677:#
F:@G #5""#<##< .#&" #4"'#4 3
# 4&5 ("( )43%,3
".# 1 (' *( 6776#
F:BG J 5 & "# ?7 ( 8A" (A8 (0(( "."
) - '< ' 1 1 * - ; *(
677=#
F:9G J5&"# 3< <1"3
(# ) - ' = ' 1 1 ( ) ;
1 *( 677=#
F:;G 4 # )" # )"3
" ) )
#
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