www.ijlret.com || Volume 02 - Issue 05 || May 2016 || PP. 69-73
DESIGN OF DIFFERENT DEVICES USING BICMOS LOGIC
Divya Bora
M.Tech VLSI
G.H.Raisoni Institute Engineering And Technology For Women, Nagpur.
Dr. U. M. Gokhale
Electronics and Telecommunication
G.H.Raisoni Institute Engineering And Technology For Women, Nagpur.
ABSTRACT-
By integrating two separate semiconductor devices that are bipolar junction transistor and CMOS transistor, in single integrated circuit devices which make a new semiconductor technology that is BiCMOS technology. As BiCMOS technology have several advantages like large load driving capabilities, low static power, fast switching, high gain, low noise and low output impedance. This paper presents the design and simulation of digital circuits such as logic gates, half adder, full adder which are basic components used for designing any other circuits such as multipliers, processors etc. These circuits are designed using BiCMOS logic and proposed designs are designed and simulated on TANNER EDA.KEY WORDS
- CMOS, Power dissipation, latch up, BiCMOS, logic gates, adders, TANNER Tools.I. INTRODUCTION
In 1930, when Lienfed and Heil introduces about MOSFETs, the history of semiconductor devices are started. To make their idea come true in reality it take 30 years, and up to the late 1980 this trend took a turn when MOS technology caught up. CMOS was finding more wide spread use due to its low power dissipation, high packing density and simple design, by the year 1990 the 90% of total MOS are covered by CMOS. In 1983 bipolar compatible process based on CMOS technology was developed and in 1990’s BiCMOS technology with both the MOS and bipolar device fabricated on the same chip was developed and studied. The main objective of introducing the BiCMOS technology is to combine BJT and CMOS technologies so as to exploit the advantages of both at the circuit and system levels. Since 1985, the state-of-the-art bipolar CMOS structures have been converging. Using this technology in reality by exploiting their advantages, now BiCMOS has become one of the dominant technologies which used for high speed, low power and highly functional VLSI circuits especially when the BiCMOS process is as similar as the CMOS process without adding any additional step to it. Because the process step required for both CMOS and bipolar are same and these steps can be shared for both of them.
II. LATCH UP IN CMOS
Traditionally uses the specific CMOS buffer circuits which have the enhanced driving capability to solve the problem driving large load. But most of the buffer configurations require a significant amount of silicon area for improvement in the signal propagation delay. The serious problem associated in CMOS devices is Latch up condition. As CMOS is having advantages of low static power consumption and the advantage of BJT that is the high current driving capabilities, the BiCMOS logic combines the both advantages into one IC.
Latch up condition
The latch-up condition is happens at any place where the required parasitic structure exists. A semiconductor goes to high current state when there is an interaction between PNP and NPN transistor causes latch up in CMOS devices. Due to latch up in any CMOS circuit cause the damage device into a loss of data or sometimes device itself. Latch up can initiate thermal runaway and can lead to destruction of a semiconductor package, chip or system when these parasitic pnpn elements undergo a high current state. Reducing the CMOS power supply voltage is a potential solution for hard latchup failures, but not soft ones [10].This condition of CMOS logic is overcome by BiCMOS logic and so using BiCMOS logic we are designing different devices.
www.ijlret.com || Volume 02 - Issue 05 || May 2016 || PP. 69-73
Fig. cross sectional vie w of CMOS inverter with Latch up circuit
III. BiCMOS
In the 1990’s modern integrated circuit fabrication technologies began to make BiCMOS a reality. For logic applications, the bipolar transistors offer designers the unique opportunity to explore the fast switching and large load drive capabilities[6]. By integrating two separate semiconductor devices that are bipolar junction transistor and CMOS transistor, in single integrated circuit devices which make a new semiconductor technology that is BiCMOS technology. Designer gets the unique opportunity to explore the fast switching and large load driving capabilities through bipolar transistors. BiCMOS technology present advantages for high performance logic devices, when the advantage of BJT technology combined with the low power and high density CMOS technology. However, CMOS technology offers high packing density, high input resistance and less power dissipation, smaller noise margin. On other hand Bipolar junction transistor technology ensures high switching and I/O speed and good noise performance, high gain, low output resistance, which are excellent properties for high-frequency analog amplifiers. Bipolar circuit fabricated in BiCMOS make it possible to amplify small signal swing with mall delay time[7]. BiCMOS technology used in Pentium, Pentium Pro and SuperSPARC microprocessors. BiCMOS inverter is constructed by following CMOS inverter by pair of BJT as shown in figure below.
Fig. BiCMOS Inverter
IV. DESIGN OF DIFFERENT DEVICES USING BICMOS LOGIC
a. Nand gateNAND gate is a universal gate, that is type of gate which used to design other gates. NAND gate is a circuit which produces an output signal unless there are signals on all of its inputs. The NAND gate using BiCMOS logic is as same as CMOS NAND gate except it is followed by a pair of BJT.
www.ijlret.com || Volume 02 - Issue 05 || May 2016 || PP. 69-73
b. Nor gateSimilar to NAND Gate NOR gate is also universal gate which produces an output signal only when there are no signals on any of the input connections. The NOR gate are designed using BiCMOS logic is as shown below.
c. Half adder
From the truth table of adder it is clear that this 1-bit adder can be easily implemented using EX-OR Gate for the output sum and an AND Gate for the carry.
d. Full adder
A full adder circuit designed with the help of two half adder circuits. The first half adder will used to add A and B to produce a partial Sum. The second half adder used to add CIN to the partial sum generated by first adder to get the final Sum output. Half adder logic produces carry thus, COUT will be an OR function of both the half-adder Carry outputs.
V. SIMULATION RESULTS
Here in this paper , the different type of devices are designed using BiCMOS logic. They are NAND gate, half adder, full adder. These designed on S-edit Tool and output is observed on W-edit tool of TANNER EDA.
a. NAND gate
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b. NOR Gatec. Half Adder
d. Full Adder
VI. CONCLUSION
BICMOS technology can be used where high speed is the prime aim. BiCMOS logic have advantages such as large load driving capabilities, low static power, fast switching, high gain, low noise and low output impedance. Here, using this BiCMOS technology we are going to design different digital devices as logic gates, half adder, full adder. These different devices are designed and simulated with TANNER Tool.
VII. REFERENCES
[1]. G.Rajeshwari, Anjo.C.A,N.Arun Kumar, “Design of High Speed Array Multiplier using BiCMOS Logic for Driving Large Load” , International Journal of Computer Applications (0975 – 8887) National conference on VSLI and Embedded systems 2013 .
www.ijlret.com || Volume 02 - Issue 05 || May 2016 || PP. 69-73
[5]. K. Ueda, H. Suzuki, K. Suda, H. Shinohara, and K. Mashiko, “A 64-bit carry look ahead adder using pass transistor BiCMOS gates,” IEEE Journal of Solid-State Circuits, 1996.
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[7]. H .Higuchi, G.kitsukawa, T.Ikeda, Y. Nishio,N. Sasaki, K. Ogiue., “ Performance And Structures Of Scaled-Down Bipolar Devices Merged With CMOSFETS”, IEEE International Conference On Electron Devices Meeting , 1984.
[8]. Mariano Aguirre-Hernandez and Monico Linares-Aranda, “CMOS Full-Adders for Energy-Efficient Arithmetic Applications”, IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol.
19, No. 4, April 2011.
[9]. Raminder Preet Pal Singh, Parveen Kumar, Balwinder Singh, “Performance Analysis of 32-Bit Array Multiplier with a Carry Save Adder and with a Carry-Look-Ahead Adder”, International Journal of Recent Trends in Engineering, Vol 2, No. 6, November 2009.
[10]. Wesley Moris, “Latchup in CMOS” , silicon engineering, Austin TX 78735USA.
