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Contemporary Logic Design

Randy H. Katz

University of California, Berkeley

The Benjamin/Cummings Publishing Company, Inc.

Redwood City, California • Menlo Park, California • Reading, Massachusetts New York • Don Mills, Ontario • Wokingham, U.K. • Amsterdam • Bonn Sydney • Singapore • Tokyo • Madrid • San Juan

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Detailed Contents

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Introduction

Introduction 1

The Process of Design 3

Design as Refinement of Representations 3 Implementation as Assembly 6

Debugging the System 8

Digital Hardware Systems 8

Digital Systems 9

The Real World: Ideal Versus Observed Behavior 11 Digital Circuit Technologies 12

Combinational Versus Sequential Switching Networks

Multiple Representations of a Digital Design 16

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Detailed Contents x v 1.3.2 Truth Tahles 18 1.3.3 Boolean Algebra 19 1.3.4 Gates 21 1.3.5 Waveforms 24 1.3.6 Blocks 25 1.3.7 Behaviors 27

1.4 Rapid Electronic System Prototyping 31

1.4.1 The Rationale for Rapid Prototyping 31 1.4.2 Computer-Aided Design Tools 32 1.4.3 Rapid Implementation Technology 33

Chapter Review 34 Further Reading 35 Exercises 35

2 Two-Level Combinational Logic

Introduction 40

2.1 Logic Functions and Switches 41

2.1.1 Boolean Algebra 41

2.1.2 Additional Kinds of Logic Gates 44 2.1.3 Justification for Logic Minimization 47

2.2 Gate Logic 49

2.2.1 Laws and Theorems of Boolean Algebra 50 2.2.2 Two-Level Logic Canonical Forms 56 2.2.3 Positive Versus Negative Logic 61 2.2.4 Incompletely Specified Functions 64

2.3 Two-Level Simplification 65

2.3.1 Motivation 66 2.3.2 Boolean Cubes 67 2.3.3 K-Map Method 70

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Detailed Contents

2.3.4 Application: Design 75

2.3.5 Process of Boolean Minimization 80

2.3.6 K-Maps Revisited: Five- and Six-Variable Functions 83

2.4 CAD Tools for Simplification 85

2.4.1 Quine-McCluskey Method 85 2.4.2 Espresso Method 89

2.5 Practical Matters 92

2.5.1 Technology Metrics 92 2.5.2 TTL Packaged Logic 93

2.5.3 Schematic Documentation Standards 96 Chapter Review 101

Further Reading 102 Exercises 103

3 Multilevel Combinational Logic

Introduction 110 3.1 Multilevel Logic 111

3.1.1 Conversion to NAND/NAND and NOR/NOR Networks 112 3.1.2 AND-OR-Invert/OR-AND-Invert Building Blocks 118

3.2 CAD Tools for Multilevel Logic Synthesis 122

3.2.1 General Concept 122

3.2.2 Factored Forms and Operations 123 3.2.3 A Tool for Multilevel Synthesis: MisII 129 3.2.4 Summary 136

3.3 Time Response in Combinational Networks 137

3.3.1 Gate Delays 137 3.3.2 Timing Waveforms 138

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Detailed Contents xvii

3.4 Hazards/Glitches and How to Avoid Them 141

3.4.1 The Problem with Hazards 141

3.4.2 Hazard Detection and Elimination in Two-Level Networks 142 3.4.3 Detecting Static Hazards in Multilevel Networks 144

3.4.4 Designing Static-Hazard—Free Circuits 145 3.4.5 Dynamic Hazards 146

3.5 Practical Matters 147

3.5.1 Elements of the Data Sheet 147 3.5.2 Simple Performance Calculations 150

3.5.3 Inputs and Outputs with Switches and LEDs 151

Chapter Review 153

Further Reading 153 Exercises 154

4 Programmable and Steering Logic

Introduction 160

4.1 Programmable Arrays of Logic Gates 161

4.1.1 Motivation for Programmable Logic 161 4.1.2 PALsandPLAs 161

4.1.3 The Difference Between PLAs and PALs 165 4.1.4 Design Examples 168

4.2 Beyond Simple Logic Gates 173

4.2.1 Switch and Steering Logic 173 4.2.2 Multiplexers/Selectors 181 4.2.3 Decoder/Demultiplexer 187

4.2.4 Tri-State Versus Open-Collector Gates 194 4.2.5 Read-Only Memories 202

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Combinational Logic Word Problems 207

1 Design Procedure 207

Case Study: A Simple Process Line Control Problem 209 Case Study: BCD-to-Seven-Segment Display Controller 212 Case Study: A Logic Function Unit 222

Case Study: An Eight-Input Barrel Shifter 224

Chapter Review 229 Further Reading 230 Exercises 231 Arithmetic Circuits Introduction 240 Number Systems 241

1 Representation of Negative Numbers 241 2 Addition and Subtraction of Numbers 244 3 Overflow Conditions 247

Networks for Binary Addition 248

1 Half Adder/Full Adder 249 2 Carry Lookahead Circuits 251 3 Carry Select Adder 256

4 TTL Adder and Carry Lookahead Components 257

Arithmetic Logic Unit Design 258

1 A Sample ALU 258 2 TTL ALU Components 262

BCD Addition 262

1 BCD Number Representation 263 2 BCD Adder Design 265

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Detailed Contents x i x

5.5 Combinational Multiplier 266

5.6 Case Study: An 8-by-8 Bit Multiplier 269

5.6.1 Theory of Operation 270 5.6.2 Implementation 271

Chapter Review 275 Further Reading 276 Exercises 277

6 Sequential Logic Design

Introduction 282

6.1 Sequential Switching Networks 283

6.1.1 Simple Circuits with Feedback 284

6.1.2 State, Clock, Setup Time, and Hold Time 288 6.1.3 The R-S Latch 292

6.1.4 The J-K Flip-Flop 293

6.1.5 Edge-Triggered Flip-Flops: D Flip-Flops, T Flip-Flops 295 6.1.6 TTL Latch and Flip-Flop Components 298

6.2 Timing Methodologies 299

6.2.1 Cascaded Flip-Flops and Setup/Hold/Propagation 300 6.2.2 Narrow Width Clocking Versus Multiphase Clocking 302 6.2.3 Clock Skew 305

6.3 Realizing Circuits with Different Kinds of Flip-Flops 306

6.3.1 Choosing a Flip-Flop Type 307

6.3.2 Conversion of One Flip-Flop Type to Another 308

6.4 Metastability and Asynchronous Inputs 309

6.4.1 Asynchronous Circuits 309

6.4.2 The Problem of Asynchronous Inputs 310 6.4.3 Metastability and Synchronizer Failure 311

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x x Detailed Contents

6.5 Self-Timed and Speed-Independent Circuits 313

6.5.1 Locally Clocked, Globally Delay-Insensitive Approach 313 6.5.2 Delay-Insensitive Signaling 313 6.6 Practical Matters 316 6.6.1 Debouncing Switches 317 6.6.2 555 Timer Component 318 Chapter Review 320 Further Reading 321 Exercises 322

7 Sequential Logic Case Studies

Introduction 329

7.1 Kinds of Registers and Counters 330

7.1.1 Storage Registers 330 7.1.2 Shift Registers 331 7.1.3 Counters 334

7.2 Counter Design Procedure 337

7.2.1 Introduction and an Example 337

7.2.2 Counters with More Complex Sequencing 341

7.3 Self-Starting Counters 343

7.3.1 Verifying If a Counter Is Self-Starting 344 7.3.2 Counter Reset 344

7.4 Implementation with Different Kinds of Flip-Flops 345

7.4.1 Implementation with R-S Flip-Flops 346 7.4.2 Implementation with J-KFlip-Flops 348 7.4.3 Implementation with D Flip-Flops 350 7.4.4 Comparison and Summary 350

7.5 Asynchronous Versus Synchronous Counters 352

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2 Synchronous Versus Asynchronous Inputs 354

Random-Access Memories 356

1 RAM Basics: A 1024 by Four-Bit Static RAM 357 2 Dynamic RAM 360

3 DRAM Variations 363 4 Detailed SRAM Timing 364

5 Design of a Simple Memory Controller 367 Chapter Review 372

Further Reading 373 Exercises 374

Finite State Machine Design Introduction 383

The Concept of the State Machine 384

1 Application: Odd or Even Parity Checker 384 2 Timing in State Machines 386

Basic Design Approach 388

1 Finite State Machine Design Procedure 388 2 Application: A Simple Vending Machine 389

Alternative State Machine Representations 395

1 Algorithmic State Machine Notation 396 2 Hardware Description Languages: VHDL 398 3 ABEL Hardware Description Language 400

Moore and Mealy Machine Design Procedure 402

1 State Diagram and ASM Chart Representations 403 2 Comparison of the Two Machine Types 404

3 Examples of Moore and Mealy Machines 406

Finite State Machine Word Problems 413

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XXÜ Detailed Contents

8.5.2 A Complex Counter 417 8.5.3 A Traffic Light Controller 421 8.5.4 Digital Combination Lock 426

Chapter Review 432 Further Reading 433 Exercises 433

9 Finite State Machine Optimization Introduction 449

9.1 Motivation for Optimization 450

9.1.1 Two State Diagrams, Same I/O Behavior 450 9.1.2 Advantages of Minimum States 451

9.2 State Minimization/Reduction 452

9.2.1 Row-Matching Method 452 9.2.2 Implication Chart Method 456

9.3 State Assignment 460

9.3.1 Traffic Light Controller 460 9.3.2 Pencil-and-Paper Methods 463 9.3.3 One Hot Encodings 468

9.3.4 Computer Tools: Nova, Mustang, Jedi 470

9.4 Choice of Flip-Flops 477

9.4.1 Flip-Flop Choice for the Four-Bit Sequence Detector 478

9.5 Finite State Machine Partitioning 479

9.5.1 Finite State Machine Partitioning by Introducing Idle States 481 Chapter Review 486

Further Reading 486 Exercises 487

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Detailed Contents xxiii

10 Finite State Machine Implementation

Introduction 496

10.1 Finite State Machine Design with Programmable Logic 497

10.1.1 Mapping a State Machine into a ROM Implementation 497 10.1.2 Application: ROM Versus PLA-Based Design 499

10.1.3 Alternative PAL Architectures 504 10.1.4 Specifying PALs with ABEL 508

10.2 FSM Design with Counters 514

10.2.1 Application: BCD-to-Excess-3 Code Converter 514

10.3 FSM Design with More Sophisticated Programmable Logic Devices 516

10.3.1 PLDs: Programmable Logic Devices 517

10.3.2 Altera Erasable Programmable Logic Devices 517 10.3.3 Actel Programmable Gate Arrays 524

10.3.4 Xilinx Logic Cell Arrays 528

10.4 Case Study: Traffic Light Controller 538

10.4.1 Problem Decomposition: Traffic Light State Machine 538 10.4.2 PLA/PAL/ROM-Based Implementation 541 10.4.3 Counter-Based Implementation 542 10.4.4 LCA-Based Implementation 544 Chapter Review 547 Further Reading 548 Exercises 549 11 Computer Organization Introduction 556 11.1 Structure of a Computer 557 11.1.1 Control 558 11.1.2 Datapath 560

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xxiv Detailed Contents

11.1.3 Block Diagram/Register Transfer 561 11.1.4 Interface to Memory 564

11.1.5 Input/Output: The Third Component of Computer Organization 566

11.2 Busing Strategies 567

11.2.1 Point-to-Point Connections 568 11.2.2 Single Bus 570

11.2.3 Multiple Buses 572

11.3 Finite State Machines for Simple CPUs 575

11.3.1 Introduction 575

11.3.2 Deriving the State Diagram and Datapath 577

11.3.3 Register Transfer Operations and Datapath Control 583 Chapter Review 590 Further Reading 590 Exercises 591 12 Controller Implementation Introduction 601 12.1 Random Logic 602 12.1.1 Moore Machine 602

12.1.2 Synchronous Mealy Machine 606

12.2 Time State (Divide and Conquer) 610

12.2.1 Partitioning the State Machine 611

12.2.2 Time State Machines for the Example Processor 611

12.3 Jump Counter 613

12.3.1 Pure Jump Counter 614 12.3.2 Hybrid Jump Counter 615

12.4 Branch Sequencers 622

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Detailed Contents xxv

12.5 Microprogramming 627

12.5.1 Horizontal Microprogramming 628 12.5.2 Vertical Microprogramming 631 12.5.3 Writable Control Store 636

Chapter Review 638 Further Reading 639 Exercises 640

Appendix A: Number Systems

Introduction 650

A.1 Positional Number Notation 650

A . l . l Decimal Numbers 651

A. 1.2 Binary, Octal, and Hexadecimal Numbers 651

A.2 Conversion Between Binary, Octal, and Hexadecimal Systems 652

A.2.1 Conversion from Binary to Octal or Hexadecimal 652 A.2.2 Conversion from Octal to Hexadecimal and Vice Versa 653 A.2.3 Conversion from Base 10 to Base 2: Successive Division 653

A.3 Binary Arithmetic Operations 656

A.3.1 Addition in Positional Notation 656 A.3.2 Subtraction in Positional Notation 658

Appendix Review 660 Exercises 661

Appendix B: Basic Electronic Components

Introduction 664 B.1 Basic Electricity 664

B.l.l Terminology 665

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xxvi Detailed Contents

B.2 Logic Gates from Resistors, Diodes, and Transistors 668

B.2.1 Voltage Dividers 668 B.2.2 Diode Logic 669

B.3 Bipolar Transistor Logic 671

B.3.1 Basic Bipolar Transistor Logic 671 B.3.2 Diode-Transistor Logic 671 B.3.3 Transistor-Transistor Logic 673 B. 3.4 TTL Circuits and Noise Margin 675

B.4 MOS Transistors 675

B.4.1 Voltage-Controlled Switches 675 B.4.2 Logic Gates from MOS Switches 677 B.4.3 CMOS Transmission Gate 679

Appendix Review 680 Further Reading 681

References

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