8051 microcontroller to FPGA and ADC interface design for high speed parallel processing systems – Application in ultrasound scanners

Full Length Article

8051 microcontroller to FPGA and ADC interface design for high speed

parallel processing systems – Application in ultrasound scanners

J. Jean Rossario Raj

, S.M.K. Rahman

, Sneh Anand

Bio Medical Engineering Unit, All India Institute of Medical Sciences, New Delhi, India

a r t i c l e i n f o

Received 17 January 2016 Revised 28 March 2016 Accepted 20 April 2016 Available online 5 May 2016

Keywords: ADC FPGA Microcontroller Serial peripheral interface Ultrasound scanner

a b s t r a c t

Microcontrollers perform the hardware control in many instruments. Instruments requiring huge data throughput and parallel computing use FPGA’s for data processing. The microcontroller in turn configures the application hardware devices such as FPGA’s, ADC’s and Ethernet chips etc. The interfacing of these devices uses address/data bus interface, serial interface or serial peripheral interface. The choice of the interface depends upon the input/output pins available with different devices, programming ease and proprietary interfaces supported by devices such as ADC’s. The novelty of this paper is to describe the programming logic used for various types of interface scenarios from microcontroller to different programmable devices. The study presented describes the methods and logic flowcharts for different interfaces. The implementation of the interface logics were in prototype hardware for ultrasound scanner. The internal devices were controlled from the graphical user interface in a laptop and the scan results are taken. It is seen that the optimum solution of the hardware design can be achieved by using a common serial interface towards all the devices.

Ó 2016 Karabuk University. Publishing services by Elsevier B.V. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

1. Introduction

Field programmable gate arrays (FPGA’s) are used in systems that require huge data throughput and parallel computing [1,2]. Microcontrollers offer major advancement as an internal and external control[3]. Microcontrollers control majority of the inter-nal devices in a typical circuit board. Moreover, majority of the application specific chips have built-in interfaces controlled through the microcontroller. Microcontrollers come with an uni-versal serial bus (USB) interface through which it is interfaced with an external device such as a host computer[4]. The interfacing of microcontroller through USB from host computer using MATLAB programming tool is studied in[5]. This provides unique advantage of integration of hardware and software[6,7]. The programming of the microcontroller is performed in traditional languages such as ‘C’ or ‘C++’[8,9]. Object oriented programming languages provide better reusability and flexibility in the firmware and software of such systems[10]. FPGA codes are written in VHSIC (very high-speed integrated circuit) hardware description language (VHDL).

Microcontrollers and FPGA’s have wide range of application in the area of instrumentation[11,12].

A study was carried out in the development of a prototype hard-ware for ultrasound scanner which required parallel processing and external control[13]. A block schematic of the microcontroller interfacing in the prototype hardware is shown inFig. 1, where the interface towards different devices such as analog to digital verter (ADC), FPGA’s, gigabit Ethernet controller (media access con-trol device or MAC), and gigabit Ethernet physical layer device (PHY) is shown. The microcontroller interface can use address/data bus interfacing which is the simplest method of interfacing as data read and write operations can be done in the byte form[14]. How-ever, this is suitable only when sufficient number of hardware pins is available in the interfacing devices. Second method uses a serial peripheral interface (SPI) which uses serial data processing for both data and address bytes[15]. This requires serialization of the data and address that makes the programming more complex and occu-pies more memory space. The third method uses serial interface that uses common serial pin for both read and write operations which is further more complex. This method requires additional byte to identify whether the intended operation is read or write.

In certain cases, the application specific chip manufacturers like ADC, dictates the type of interface to be used for the microcon-troller interfacing. Hence, this aspect also needs consideration for

http://dx.doi.org/10.1016/j.jestch.2016.04.004

2215-0986/Ó 2016 Karabuk University. Publishing services by Elsevier B.V.

This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

⇑Corresponding author at: Room No. 299, 2nd Block, Centre for Bio-Medical Engineering, Indian Institute of Technology, New Delhi, India.

E-mail address:[email protected](J. Jean Rossario Raj). Peer review under responsibility of Karabuk University.

Contents lists available atScienceDirect

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an International Journal

interfacing. When multiple devices are programmed through a common programming bus, chip select (CS) is used to decide the device to be programmed. In such case, signals for the input/output (IO), clock etc., are common across all the devices.

The novelty of this paper is a study on the different methods used for interfacing between the microcontroller and parallel pro-cessing devices such as FPGA’s and data converters. The paper also compares and studies the best algorithm for different implementa-tion condiimplementa-tions.

2. Materials and methods

2.1. Choosing of the microcontroller and FPGA

The microcontroller used was C8051F340 from silicon laborato-ries. It operates at a maximum speed of 48 MHz with 4k of on-board random access memory (RAM) and 64k flash memory. The microcontroller has integrated USB receiver and USB controller. It has 48 IO pins configured as five IO buses with eight IO’s each. The microprocessor in the ultrasound scanner prototype interfaces with a bank of ADC’s and FPGA’s. The microprocessor firmware is written in C language[16]. One IO bus is used as the programming header for programming the microcontroller through the USB from the host computer. The transfer of firmware to the microcontroller is through this header using the program-mer hardware of m/s silicon labs.

For logic emulation systems the FPGA provides faster computa-tion as compared to software simulacomputa-tion[17]. The logic designs are customised for high performance in different types of applications

[18]. In multimode system, the FPGA’s yield significant hardware savings and provides generic hardware in[19]. In order to meet the above requirements, Xilinx FPGA, Spartan 3E (XC3S500E_208) with the following specifications is chosen. The FPGA has 172 I/O Pins and 216K Blocks of RAM. Low voltage differential signalling (LVDS) is used for interfacing with high voltage pulser and receiver chips. The speed of the IO Bus is 622Mbps, with EEPROM having master–slave/JTAG (joint test action group) programming headers.

2.2. Microcontroller – FPGA interface using address/data bus

The microcontroller to transmit side FPGA (Tx-FPGA) interface was implemented using address/data bus method as shown in

Fig. 1. This method was chosen since the FPGA and microcontroller

Micro controller USB Interface Rx FPGA ADC SPI Interface Serial Interface Tx FPGA Gigabit Ethernet Phy Address / Data bus Interface MDIO Interface Gigabit Ethernet Controller Inline control

Fig. 1. Block schematic of the experimental setup.

Microcontroller C8051F340 FPGA

Spartan 3E XC3S250E_208

8 Bit address Bus

8 Bit Data Bus

READ WRITE CHIP SELECT FPGA Program to read/write from MC MC Program to Read / Write to FPGA

Fig. 2. Block schematic of the microcontroller – FPGA address/data bus interfacing.

Assign Address Pins with Address Byte

Chip Select = 0 Configure Port mode =

OUT e.g. P4MDOUT=0xFF

Assign Data to data pins Write Pin = 0 Wait Write Pin = 1 Chip Select = 1 Address = 0xFF Data = 0xFF Start End Start Assign Address Pins

with Address Byte

Chip Select = 0 Read Pin = 0 Configure Port mode =

IN e.g. P4MDOUT=0x00

Read Data from data pins Read Pin = 1 Chip Select = 1 Address = 0xFF Data = 0xFF End

Fig. 3. Flow chart of microcontroller firmware for address/data bus interfacing – Write and Read operations.

Start End Continue to Next Address Read Register-0 & Move Data

to Data Bus

Continue to Next Address Read Data Bus

& Move Data to Register-0 Yes Yes Yes No _No Yes No No Write Pin = 0 &

Chip Select = 0

Read Pin= 0 & Chip Select = 0

Address = 0

Address = 0

Fig. 4. Flow chart of FPGA program for address/data bus interfacing.

Microcontroller C8051F340 Rx FPGA Spartan 3E XC3S250E_208 MOSI MISO CHIP SELECT FPGA Program to read/write from MC SLAVE MC Program to Read / Write to FPGA

MASTER CLOCK

had sufficient number of IO pins i.e. 19 pins. Hence, to make the program logic simple, address/data bus method of interfacing was used. The interconnection between the FPGA and the micro-controller used 8-bit address bus, 8-bit data bus, read, write and CS as shown inFig. 2. The address bus is simplex i.e. from micro-controller to the FPGA whereas the data bus is duplex. The logic 0 or low in read or write pin indicates that the proposed operation is read or write.

The flow chart of the microcontroller program for read and write operations of the microcontroller is given inFig. 3. In the write operation, the data bus uses OUT mode where as in read

operation, the data bus uses IN mode. This is configured using the P4MDOUT configuration depending upon the port being con-figured. CS is pulled low depending upon the device to be pro-grammed. Read or write pins are made active low depending upon the read or write operation. The address byte is sent to the address bus pins. In case of write operation, data byte is also sent to the data bus pins whereas in read operation, data byte is read from the data bus pins.

The FPGA logic for the RW operations is presented in Fig. 4. FPGA logic waits for the CS pins to be active low. FPGA initiates RW operation during the falling edge of the CS. When write pin

Count > 8 Count = 0 Increment counter Next Bit = 0 MOSI = 0 MOSI = 1 Exit

FPGA Write Byte Sub Routine Clock = 1 Clock = 0 Del ay No Yes No Yes Count > 8 Count = 0 Increment counter Data = Data | 0 Data = Data | 1 Exit

FPGA Read Byte Sub Routine Clock = 1 Clock = 0 Del ay No Yes MISO = 0 Yes No Clock = 0 MOSI = 0 Chip Select = 0 Start Stop Clock = 0 MOSI = 0 Chip Select = 1 FPGA Write – Address Byte Read / Write Operation FPGA Read – Data Byte FPGA Write– Data Byte Write Read FPGA Write – 01 Byte (Write indicator ) FPGA Write – Address Byte FPGA Write – 00 Byte (Read indicator )

Fig. 6. Flow chart of microcontroller firmware for SPI bus interfacing towards FPGA.

Rising Edge of Clock

Count = 0

Read Data Bit from MOSI to LSB of logic vector Increment counter Count >= 16 Count = 24 Read Operation LSB=1, Read LSB=0, Write No Yes Yes Yes Yes Yes Yes No No No No No

Move last byte to address logic vector

Move previous byte to address logic vector

Move last byte to Data logic vector Move data from

address location Register to data logic vector Rising Edge of Clock Move MSB of data to MISO Shift data logic

vector Count = 0

Count = 8 Increment counter

Move data from data logic vector to

address location register Rising Edge of Clock No Yes No Yes Count >= 8

goes to active low, FPGA reads the address & data from the address & data pins and moves data to the respective register location. Similarly, in the read operation, when the read pin goes to active low, FPGA reads the address from the address pins. The data from the corresponding address location register is placed in the data bus pins.

2.3. Microcontroller – FPGA interface using SPI bus

In the receive side FPGA (Rx-FPGA), sufficient IO pins were not available. Hence, address/data bus type of interfacing followed in Tx-FPGA was not used. Here, serial interface using SPI bus was used. The block schematic of the microcontroller to Rx-FPGA inter-face is given inFig. 5. In this method, the microcontroller is acting as the master and the Rx-FPGA is acting as the slave. The serial address/data path from microcontroller to FPGA is referred as mas-ter out slave in (MOSI) and from FPGA to microcontroller is

referred as master in slave out (MISO). The other interface IO’s includes the CS and the clock, which are supplied by the microcon-troller. The major challenge in SPI is to send and receive the data in serial format, i.e., bit by bit.

The microcontroller program flowchart for SPI is given inFig. 6. An active low CS signal is used to identify the FPGA device to be written. The microcontroller uses the write byte, read byte, sub-routines ofFig. 6for serial write, and read operations. The time duration for toggling of the clock pin between the active low and active high is controlled by the delay. In each clock, one bit is moved to the MOSI pin during the write operation and one bit is read from the MISO pin during the read operation. This cycle is continued for 8 bits. In the read/write (RW) operation, one byte of RW flag is written to the FPGA indicating the type of operation. Further, in write operation, address and data bytes are written whereas in read operation, address byte is written and data is read from the MISO pins.

The flow chart of the FPGA program is given inFig. 7. When CS becomes active low, FPGA reads from MOSI pin bit by bit during the rising edge of the microcontroller clock. When FPGA completes reading one byte, based on the byte flag value, it decides whether the operations is read or write. FPGA further reads the address byte. For read operation, FPGA uses a logic vector for temporary storage of the address value. FPGA moves the data from the register at the address location to the MISO pin bit by bit. In write opera-tion, FPGA reads the next byte as well. FPGA moves the data value to a temporary logic vector. Further FPGA writes the data value to the register at the address location.

2.4. Microcontroller – ADC interface using serial bus

In the developed prototype of the ultrasound scanner, AD9272 from M/s Analog Devices is used as the receiver which has the complete analog front end comprising of the low noise amplifier (LNA), variable gain amplifier (VGA), time gain compensation (TGC) and the ADC[20]. Each AD9272 comprises of eight channels. Four such AD9272’s are used in the design. The same data IO and clock from the microcontroller is used for all the four ADC’s. The

Microcontrol ler C8051F340 CLOCK Data IO ADC-1 ADC-2 ADC-3 ADC-4 Chip Select 1 Chip Select 2 Chip Select 3 Chip Select 4

Fig. 8. Block schematic of the microcontroller – ADC serial bus interfacing.

Count = 0

Increment counter

Return Port Mode = OUT

Next Bit to be sent = 1 Data IO = 1 Data IO = 0 Clock = 0 Delay Clock = 1 Delay Count > 8

Microcontroller Write Byte Sub Routine

No No Yes Yes Count = 0 Increment counter Return Port Mode = IN Data IO = 1 Data = Data | 1 Clock = 0 Delay Clock = 1 Delay Count > 8

Microcontroller Read Byte Sub Routine

No No Yes Yes Data = Data | 0 Chip Select Stop Microcontroller Write – Address Byte Read / Write Microcontroller Write – Data Byte

Microcontroller Read – Data Byte

Chip Select Start

Composite Flow chart Microcontroller

Write – Read/Write Flag

chips are selected for command execution based on the CS. The block schematic of interconnection of microcontroller to the ADC’s is given inFig. 8.

The flowchart of the microcontroller firmware for the interface with ADC’s is given in Fig. 9. The algorithm uses read byte and write byte sub-routines for RW operations respectively. Since the same pin of the microcontroller is used for both send and receive,

the port mode is changed to IN or OUT suitably. The sub-routine writes or reads bit by bit for a complete byte using the IO pin. In the composite flowchart, RW flag is written first followed by the address, which gives an indication of the forthcoming operation. In case of read, the microcontroller reads the data byte or in case of write, the microcontroller writes the data byte as per the logic of the sub-routine. A delay is given for performing the read or write operation. The operation is bit by bit.

3. Results and discussions

A prototype developed for the ultrasound scanner with USB interface is shown inFig. 10. The prototype has the silicon labora-tories C8051F340 microcontroller, Xilinx FPGA’s and ADC’s (AD9272) from analog devices. It has the microcontroller program-ming header as well as the FPGA programprogram-ming headers. The pro-gramming of the microcontroller as well as the FPGA’s was performed through the headers. The prototype is connected to the laptop graphical user interface (GUI) through the USB interface. A GUI is developed using MATLAB software for the configuration of different parameters of the devices. The GUI is shown inFig. 11. Through this GUI, the different parameters of the FPGA’s and ADC’s are configured through the microcontroller. The transmit frequency, pulse burst width, selection of the channels for the transducer exci-tation etc., are selected from the GUI. This configures the Tx-FPGA for controlling these operations. This control from microcontroller to the Tx-FPGA is through the address/data bus parallel interface. Tx FPGA

Rx FPGA Microcontroller

Receiver & ADC Ethernet MAC Ethernet PHY Microcontroller Programming header Tx FPGA Programming header Transmit Pulsers

Fig. 10. Ultrasound scanner prototype hardware.

ADC configuration

Pulser channel enabling

Read or Write Configuration Register Values

Command Buttons

_{Tx & Rx-FPGA}

configurations

A channel is selected as shown inFig. 11. Configure FPGA command, transfers the HEX values to the microcontroller, which in-turn writes the Tx FPGA registers through the parallel interface. The Tx-FPGA generates the required enable and excitation pulses. The output pulse waveforms of the transmit section used for exciting the ultrasound transducer array is shown inFig. 12showing the pos-itive and negative trail of high voltage pulses.

Similarly, AD9272 parameters like the LNA Gain, VGA Gain, AAF upper and lower cutoff frequencies, generation of test pattern etc.,

are controlled by programming the ADC’s through the microcon-troller as shown inFig. 11. The control to the ADC is through serial interface. In addition, the control to the Rx-FPGA is through SPI interface. In addition, the start and stop of scan is controlled by the configuration of the transmit and receive FPGA’s. Upon start of a scan, the Tx-FPGA, excites the selected channels. The Rx-FPGA receives the data from the ADC’s, convert the data into pack-ets and it is sent to the laptop over the Ethernet interface. The Eth-ernet packets received from the prototype is shown inFig. 13.

The stop scan disables the channels and stop sending the Ether-net data packets. Thus by programming control through the micro-controller, the developed hardware is able to be controlled very effectively. The image was taken using a linear array transducer probe working at 4 MHz. The receive beamforming, image and video processing algorithms like smoothening, sharpening, his-togram equalization etc., were performed in MATLAB graphical user interface. The receive beamforming required delay and sum algorithm for the simultaneously received channels. The image obtained with a lab phantom indicating the position of the inclu-sion as well as the depth of the phantom is given inFig. 14.

The comparison of the three methods of microcontroller inter-facing is given inTable 1.

It is seen fromTable 1that serial interfacing is the most plex but most efficient in respect of pin usage and can be com-monly used across all the devices. Usually execution time is not an important criterion as the microcontroller interface is used for machine control. However, in case the microcontroller interface is used for data transfer, address/data bus configuration is pre-ferred. Hence, the actual type of interfacing required is to be decided after weighing all the pros and cons of different interfacing methods.

Positive Pulse Trail of Excitation pulses

Negative Pulse Trail of Excitation pulses

Fig. 12. Output pulse waveform based on microcontroller FPGA control.

Data length

UDP Protocol

Port 104 – ACR-NEMA

4. Conclusion

The most important part of the development of the firmware was in the development of the interface programs that was suit-able for the interfaces supported by the application specific device as well as the availability of pins in the interface devices. Interface design is the most important step in the use of general-purpose devices like microcontrollers and FPGA’s for application specific usages and control. The use of general-purpose microcontrollers and FPGA’s will make the hardware miniaturised and cost effective, which is an essential requirement for telemedicine application

[21]. With the innovative approaches, it was possible to develop highly configurable, scalable and flexible FPGA based ultrasound systems[14,22]. The development of these interfaces helped in the miniaturization of the hardware, thus enabling the hardware to be used for telemedicine applications[1,23,24]. The FPGA based implementation has helped in the hardware to be operated at high frame rates of the order of 8000[25,26].

One important conclusion arrived from the study after using different types of interfaces was that it is always preferable to use one type of interfacing across multiple devices. In this study

of microcontroller interface with FPGA’s and ADC’s, the best option will be to go for serial interface compatible with ADC for all types of devices. This will have the following pros and cons. The micro-controller program becomes simple as single interface logic can be used for all types of devices. This will also reduce the number of microcontroller pins used. This will further reduce the number of FPGA pins required for control also. However, the FPGA program will be very complex and FPGA will require more storage space. But same FPGA interface code can be used for both the FPGA’s.

While developing the different interfaces the main aspect of consideration was the ease of programming. As a future step, all the interfaces can be made common so that the microcontroller program further simplifies even though there would be more com-plications in the FPGA program algorithms. This could further improve the design architecture.

Acknowledgment

The authors thank Department of Science and Technology, Government of India for providing financial support for this project.

Reflection by Inclusion and inside air gaps

Reflection from bottom surface

Phantom with inclusion used for the evaluation

Fig. 14. Ultrasound image of a phantom with inclusion captured using the prototype. Table 1

Comparison of the microcontroller interfacing methods.

Address/data bus SPI bus Serial bus

Hardware pins required to interface Address: 8 Clock: 1 Clock: 1

Data: 8 MOSI: 1 Data: 1

Read: 1 MISO: 1 CS: 1

Write: 1 CS: 1 Total: 3

CS: 1 Total: 4

Total: 19

Minimum active clock cycles to execute write instruction 1 RW flag: 8 RW flag: 2

Data: 8 Data: 8

Address: 8 Address: 8

Total: 24 Total: 18

Minimum active clock cycles to execute read instruction Write address: 1 RW flag: 8 RW flag: 2

Read data: 1 Write address: 8 Write address: 8

Total: 2 Read address: 8 Read address: 8

Read data: 8 Read data: 8

Total: 32 Total: 26

Execution time Fast Slow Slow

Reliability High Medium Low

Program simplicity Simple Medium Complex

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