CURRENT-MODE CMOS SEQUENTIAL MULTIPLE-VALUED LOGIC CIRCUITS

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by Fatma Sarıca

B.S., Electronics and Communication Engineering, Istanbul Technical University, 2001 M.S., Electronics Engineering, Boğaziçi University, 2004

Submitted to the Institute for Graduate Studies in Science and Engineering in partial fulfillment of

the requirements for the degree of Doctor of Philosophy

Graduate Program in Electronics Engineering Boğaziçi University

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CURRENT-MODE CMOS SEQUENTIAL MULTIPLE-VALUED LOGIC CIRCUITS

APPROVED BY:

Prof. Avni Morgül ………

(Thesis Advisor)

Prof. Günhan Dündar ………

Prof. Ali Toker ………

Prof. Oğuzhan Çiçekoğlu ………

Assist. Prof. Faik Başkaya ………

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ACKNOWLEDGEMENTS

I would like to express my sincere gratitude to my thesis supervisor, Prof. Avni Morgül for his invaluable guidance, patience, motivation, advice and contributions throughout this study. His guidance helped me in all the time of research and writing of this thesis. It was really a pleasure for me to work with him.

I would like to thank Prof. Günhan Dündar and Prof. Ali Toker for their insightful comments, valuable suggestions, and serving my thesis committee.

I am also thankful to Prof. Oğuzhan Çiçekoğlu and Assist. Prof. Faik Başkaya as being part of my thesis committee.

My deepest gratitude goes to my mother, for her care and support throughout my life; this dissertation is simply impossible without her. I have no suitable word that can fully describe her everlasting love to me.

I would like to express my heart-felt gratitude to my family, Kemal and Berat, for they bring meaning to my life.

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ABSTRACT

CURRENT-MODE CMOS SEQUENTIAL MULTIPLE-VALUED

LOGIC CIRCUITS

The use of circuits with more than two logic levels, named as Multiple-Valued Logic (MVL) circuits, have a potential for reducing chip area consumed by interconnection wiring and functional units in Very-Large Scale Integration (VLSI). Many logical and arithmetic functions have been shown to be more efficiently implemented with multiple-valued logic in terms of number of operations, gates, transistor count and signal lines etc. However, in spite of their potential advantages, developments in multi-valued systems are not satisfactory. It is still a complicated task to design a system for processing a signal in a multi-valued manner despite considerable effort. Multi-valued logic circuits can be designed in current mode or voltage mode. Due to the limited supply voltages, higher radices could not be obtained using voltage mode circuits. On the other hand, current mode circuits have the advantages of current scaling, copying and sign changing with a simple current mirror, but unlike binary logic circuits, they are not self-restored. In this study, current-mode sequential logic circuits are designed and analyzed. Multiple-valued counterparts of the well-known flop structures are discussed and a new type of flip-flop circuit, named AB, is proposed. The proposed circuit is used in various counter and random seque ntial circuit designs. Circuit schematics and simulation results are presented. In addition, a multiple-valued and binary counter designs that are using D-type flip-flops (the only flip-flop that has the same output equations for both MVL and binary) are compared in terms of various VLSI design criteria.

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ÖZET

AKIM-MODLU CMOS ARDI

Ş

IL ÇOK

DEĞERLİ

MANTIK

DEVRELER

İ

İkiden fazla mantık seviyesine sahip devreler, Çok Değerli Mantık (ÇDM) devreleri, çok büyük çapta tümleştirilmiş devrelerde, ara bağlantılar ve fonksiyonel kısımlar tarafından harcanan kırmık alanını azaltma potansiyeline sahiptirler. Birçok mantık ve aritmetik fonksiyonun işlem sayısı, kullanılan kapı ve transistör adedi gibi açılardan ÇDM devreleri ile daha etkin bir biçimde gerçekleştirilebileceği gösterilmiştir. Bununla birlikte, potansiyel faydalarına rağmen çok seviyeli sistemlerdeki gelişmeler tatmin edici değildir. Dikkate değer çabalara rağmen, bir sinyali çok değerli bir şekilde işleme için bir sistem tasarlamak halen karmaşık bir iştir. ÇDM devreleri akım-modlu veya gerilim-modlu olarak gercekleştirilebilirler. Sınırlı besleme gerilimleri nedeniyle, gerilim-modlu devreler kullanılarak yüksek tabanlar elde edilememiştir. Diğer taraftan, akım-modlu devreler basit bir akım aynası kullanarak akım ölçekleme, kopyalama ve işaret değiştirme avantajlarına sahiptirler, fakat ikili mantık devrelerinin aksine, kendi akım seviyelerini düzenleyemezler. Bu çalışmada, akım-modlu ardışıl mantık devreleri tasarlandı ve analiz edildi. Bilinen iki-durumlu devrelerin çok değerli karşılıkları tartışıldı ve yeni bir iki-durumlu devre yapısı olarak AB iki-durumlu devresi önerildi. Önerilen devre farklı sayıcı tasarımlarında ve rastgele bir ardışıl devre tasarımında kullanıldı. Devre şemaları ve benzetim sonuçları sunuldu. Buna ek olarak, D-tipi iki-durumlu (ÇDM ve iki seviyeli mantık devreleri için aynı çıkış denklemine sahip tek iki-durumlu) devre kullanılarak tasarlanan çok değerli ve iki seviyeli sayıcı devreleri çeşitli çok büyük capta tümleştirme kriterlerine göre karşılaştırıldı.

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LIST OF FIGURES

Figure 2.1. Addition operation in current-mode MVL. ... 9

Figure 2.2. n-type and p-type current mirrors. ... 10

Figure 2.3. Multiplying a current by a constant k. ... 10

Figure 2.4. Current redirecting circuit. ... 10

Figure 2.5. Using MVL circuits in binary designed systems. ... 11

Figure 2.6. Current comparator circuit. ... 12

Figure 2.7. Encoder circuit. ... 13

Figure 2.8. Decoder circuit. ... 13

Figure 2.9. Complement operator. ... 14

Figure 2.10. Truncated difference operator. ... 15

Figure 2.11. Lower threshold circuit. ... 16

Figure 2.12. Window literal operator. ... 17

Figure 2.13. Clockwise cyclic operator. ... 18

Figure 2.14. min circuit introduced in [69]. ... 19

Figure 2.15. Multi-input min circuit [52]. ... 20

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Figure 2.17. Multi-input max circuit [48]. ... 22

Figure 3.1. Block diagram of a seque ntial circuit. ... 28

Figure 3.2. Current-mode CMOS quaternary latch circuit. ... 30

Figure 3.3. Restoration stage. ... 31

Figure 3.4. 8-level latch circuit based on level restoration circuit of reference [84]. ... 33

Figure 3.5. Input, output and clock signal waveforms of simulated 8-level latch circuit. ... 34

Figure 4.1. Block diagram of the AB flip-flop. ... 40

Figure 4.2. A and B input signals for the AB flip-flop. ... 41

Figure 4.3. Clock and Q output signals for the AB flip-flop. ... 41

Figure 4.4. Layout of AB flip-flop. ... 42

Figure 4.5. Counting diagram of 1-digit modulo-4 counter. ... 43

Figure 4.6. 1-digit modulo-4 synchronous counter block diagram. ... 44

Figure 4.7. 1-digit modulo-4 synchronous counter clock and output signals. ... 45

Figure 4.8. Counting diagram of 2-digit modulo-16 counter. ... 46

Figure 4.9. 2-digit modulo-16 synchronous counter block diagram. ... 49

Figure 4.10. 2-digit modulo-16 synchronous counter clock and output signals. ... 49

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Figure 4.12. 2-digit modulo-16 ripple counter block diagram. ... 51

Figure 4.13. Clock signals for the first and second flip-flop of 2-digit modulo-16 ripple counter. ... 51

Figure 4.14. 2-digit modulo-16 ripple counter output signals. ... 52

Figure 4.15. State diagram of the new seque ntial circuit. ... 53

Figure 4.16. Block diagram of the new sequential circuit. ... 57

Figure 4.17. x and clock signal inputs of the new sequential circuit. ... 58

Figure 4.18. Q1 and Q2 outputs for the new sequential circuit. ... 58

Figure 4.19. Binary equivalent circuit of the same new sequential circuit. ... 61

Figure 5.1. Multiple-valued D-type flip-flop. ... 63

Figure 5.2. Counting diagram for 1-digit modulo-8 multiple-valued and 3-bit modulo-8 binary counter. ... 63

Figure 5.3. Block diagram of 1-digit modulo-8 multiple-valued counter. ... 64

Figure 5.4. Output and clock signal waveforms for 1-digit modulo-8 counter circuit. ... 65

Figure 5.5. Layout of 1-digit modulo-8 counter. ... 65

Figure 5.6. Binary XOR. ... 66

Figure 5.7. Binary D flip-flop. ... 66

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LIST OF TABLES

Table 2.1. Current levels of multi-valued current-mode signals. ... 8

Table 2.2. Truth table for complement operator. ... 14

Table 2.3. Truth table for lower and upper threshold operations. ... 16

Table 2.4. Truth tables of clockwise cyclic and counter clockwise cyclic operators. ... 17

Table 2.5. Truth table for min operator. ... 19

Table 2.6. Truth table for max operator. ... 21

Table 2.7. Truth table of a 4-valued, 2-variable example function. ... 23

Table 2.8. Rearranged truth table of the given example function. ... 24

Table 3.1. General transition table of R-S type multistable. ... 35

Table 3.2. General transition table of D- type multistable. ... 36

Table 3.3. General transition table of J-K type multistable. ... 37

Table 3.4. General transition table of T-cyclic type multistable. ... 38

Table 4.1. General transition table of the AB flip-flop. ... 40

Table 4.2. Power and delay measurements of AB flip-flop. ... 42

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Table 4.4. Possible flip-flop input values for specified present-state and next-state values of 1-digit modulo-4 counter. ... 44 Table 4.5. Minimization maps for the 2-digit modulo-16 counter. ... 46 Table 4.6. Possible flip-flop input values for specified present-state and

next-state values of 2-digit modulo-16 counter. ... 47 Table 4.7. Possible flip-flop input values for specified present-state and

next-state values of the new sequential circuit. ... 54 Table 4.8. Minimization maps of first AB flip-flop for the new sequential circuit. .. 55 Table 4.9. Minimization maps of second AB flip-flop for the new sequential

circuit. ... 56 Table 4.10. Possible flip-flop input values for specified present-state and

next-state values of new sequential circuit for the binary JK flip-flop. ... 59 Table 5.1. Flip-flop input values for specified present-state and next-state values

of 1-digit modulo-8 counter using D-type flip-flop. ... 64 Table 5.2. Power and delay measurements of modulo-8 counters. ... 68

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LIST OF SYMBOLS

[a,b] Closed interval with boundaries a and b

,

c c

b b

a a c-valued upper, lower threshold operation on a at value b Ap Parameter p-associated area statistical variation parameter Cox Oxide capacitance of a MOS transistor

D Total distance of an index from other indices

Ib Reference current

KP SPice process transconductance parameter

n Number of variables

r Radix

Sp Parameter p-associated distance statistical variation parameter thu Upper threshold operation

thl Lower threshold operation

VGS/DS (Gate/drain)-to-source voltage of a MOS transistor

VTO SPice zero-bias threshold voltage parameter of a MOS transistor <x> Restored value of x to a predefined logic level

x+ , x- Successor and predecessor operators

a b

x Window literal for interval [a,b] y

x→ , y

x← Clockwise and counter clockwise operators

x Complement of x

∆x Variation in x

∈ Member of

,

.

Min operator

, + Max operator

β Transconductance of a MOS transistor

γ SPice body-bias parameter of a MOS transistor

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µ Mobility

φ SPice surface potential parameter of a MOS transistor

Ξ Truncated difference operator σ/σ2

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LIST OF ACRONYMS/ABBREVIATIONS

CCWC Counter Clockwise Cyclic

CMOS Complementary Metal Oxide Semiconductor

CWC Clockwise Cyclic

IC Integrated Circuit

LSD Least Significant Digit

LTA Loser-Takes-All

MOS Metal Oxide Semiconductor MSD Most Significant Digit MVL Multiple-Valued Logic VLSI Very Large Scale Integration

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1. INTRODUCTION

The growth in the IC industry showed an exponential trend over the last decades. As the number of transistors per unit area increases, the industry has faced some new

problems. The major problem that the industry must solve to maintain this growth is the interconnections (both on chip and between chips) and the routing of these interconnections. The silicon area that used for these interconnections may be greater than that used for the active logic elements [1].

The use of circuits with more than two logic levels has been offered as a solution to these interconnection problems. Such circuits, named as Multiple-Valued Logic (MVL) circuits, have a potential for reducing chip area consumed by interconnection wiring and functional units in Very-Large Scale Integration (VLSI) [2]. Applying signals having more than two levels to a single wire reduces the number of wires for the same range of data, and this reduction results in a decrease in number of required IC pins. As the interconnection length and number of wires used is reduced, the space between any two wires increases without increasing the total silicon area, leading to a decrease in resistance and capacitance of contacts and interconnections, and the interconnection delay can be greatly decreased [3].

However, in spite of their potential advantages, developments in multi-valued systems are not satisfactory. It is still a complicated task to design a system for processing a signal in a multi-valued manner despite considerable effort. Difficulties start with the implementation of the functional basic set and go on with simplification of logic expressions [4].

Multi-valued logic circuits can be designed in current mode or voltage mode. Due to the limited supply voltages, higher radices cannot be obtained using voltage mode circuits. On the other hand, current mode circuits have the advantages of current scaling, copying and sign changing with a simple current mirror, but unlike binary logic circuits, they are not self-restoring.

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1.1. Literature Survey

In 1921, Post [5] gave a definition of n-valued logic that was a generalization of the usual 2-valued logic. Later, Webb [6] and Rosenbloom [7] made studies on development of Post algebras and their properties. Attempts for realizing multi-valued switching circuits became visible a couple of decades after Post’s definition.

Until 1950’s, switching circuit theory has concentrated mainly on two-valued logic systems. The main reason of this interest is that logical devices are two-state and the mathematical model –Boolean algebra- cannot be extended to other integer-valued logic systems. The idea of building systems from multistable devices appears in 1950’s. Berlin [8], Lee and Chen [9], and Lowenschuss [10] have made first studies about non-binary switching systems. Hartmanis [11] suggested that in some respects linear systems built from multistable devices maybe superior to the conventional two-state systems and their practical implementation is feasible.

In 1960’s, researchers studied to devise a set of basic functions and to develop algebra such that functions of arbitrary complexity may be represented in terms of simple algebraic combinations of the basic functions. Allen and Givone [12] and Vranesic et al. [4] introduce a minimization technique for multiple-valued logic systems. Minimization is an important topic in multiple-valued logic and researchers are still studying to find new algorithms.

In 1970’s, sequential multi-valued logic has attracted great attention. Researchers have focused their attention on the determination of general excitation tables and input equations for different type multistables. General next-state equation of a JK-type multistable first introduced by Wojcik [13], and extended for arbitrary radix by Acha and Huertas [14]. T-cyclic type multistable was introduced by Acha and Huertas [15], D type by Huertas and Acha [16], and RS type by Acha and Huertas [17]. Wills [18] made a detailed analysis about R-flop triggering modes. Several design examples are introduced by Sintonen [19] and Mouftah and Jordan [20]. Ternary flip-flop and sequential circuit designs based on modification of device threshold voltages and hybrid designs were introduced by Prosser et al. [21], Wu and Prosser [22], and Webb et al. [23] in later years.

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Many logical and arithmetic functions have been shown to be more efficiently implemented with multiple-valued logic, i.e. fewer operations, gates, transistors, signal lines, etc. are required. Multiplier circuits introduced by Kawahito [24-25], Chan et al. [26], Tanno et al. [27], Chu and Current [28], Hanyu and Kameyama [29], Ishizuka et al. [30], Tagaki et al. [31], Herrfeld and Hentschke [32], adder circuits by Wakui and Tanaka [33], Manzoul et al. [34], Radanovic and Syrzycki [35], Mingoto [36], PLA’s by Pelayo et al. [37], decoders by Prieto et al. [38] are some examples.

As the technology approaches to minimum dimension, we need an alternative way to achieve high-density memories. Multiple-valued logic is the way of encoding multiple states of information in a single memory cell. In 1980’s quaternary ROMs are introduced by Adlhoch [39], Rich et al. [40], etc. and quaternary logic used in processor design. Various current mode and voltage mode memory circuits introduced by Cilingiroglu and Ozelci [41], Lee and Gulak [42], Current [43] and latch circuits by Current [44-46], can be found in the literature. Main advantage of these latch circuits is that they are not only holding the output current, but also restoring the output current level to a predefined logic levels. This property helps in solving one of the main problems of current-mode CMOS MVL circuits.

In 1990’s, similarities between multiple-valued logic and fuzzy logic were recognized. Min/max circuits are the basic building blocks in both multi-valued logic and fuzzy logic. Conventional min/max circuits accept two input values and produce an output. Although they have compact structures and their performance is quite well, only two input values become a problem when we have an array of input values. Lazzaro et al. [47] offered a solution to this problem by winner-take-all circuits. This type of circuits selects the maximum of the currents applied to its inputs. This circuit was improved by the researchers Baturone et al. [48], Ota and Wilamowski [49], Patel and DeWeerth [50], Sekerkiran and Cilingiroglu [51], Huang et al. [52], Günay and Sánchez-Sinencio [53], Wilamowski and Jordan [54], Carvajal et al. [55], Aksin [56], Pojanasuwanchai et al. [57], Keawconthai et al. [58], Yotingoravong et al. [59], Nia et al. [60], and high speed, high precision current/voltage mode winner/loser-take-all circuits were produced.

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Toda y, almost every type of binary logic circuits can be realized as multiple-valued approach like adder/multiplier circuits [24-35], memory circuits [41-43], sequential circuits [13, 20-22, 61-62], decoders/encoders [38, 63], current/voltage comparators [64], programmable devices [37] and etc. and some of these circuits can be compatible with their binary counterparts.

1.2. Outline of the Thesis

The current study is an attempt to close the gap in the sequential multiple-valued logic design area. Current-mode CMOS circuits are chosen for the implementation of the circuits due to their potential advantage of higher radix implementation and realizing algebraic sum operation with no cost on system design.

In this section, the idea of multiple-valued logic is explained and its development over decades is discussed. Several MVL applications of combinational and sequential logic are introduced.

In the next section, basic multiple-valued logic elements and combinational logic operator designs are introduced. Encoding and decoding operations that performs binary-to-MVL and MVL-to-binary conversions are presented. Functional completeness of MVL algebra and mismatch analysis is discussed.

The third section focuses on sequential circuits and multiple-valued latch circuits. Input-output equations of well-known binary flip-flops, and their multiple-valued logic counterparts, input-output relations and truth tables are introduced.

The fourth section introduces a new flip-flop circuit, called AB flip-flop. It is a two-input single- output MVL flip-flop circuit with successful state transitions for all the two- input-output current combinations. Input-input-output equations and simulation results are studied carefully and the flip-flop circuit is used in several synchronous and asynchronous counter circuit design. In addition, a totally random state equation is realized using this flip-flop and binary JK flip-flops, the total area consumption of the circuits are compared.

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The fifth section is about comparison of multi-valued and binary sequential logic according to various VLSI design criteria (power consumption, transistor count, etc). D-flip-flop (the only flip-flop that has the same input-output equation for binary and multiple-valued logic) is chosen for the realization to ensure a fair comparison.

Last section concludes the study and compares the outcomes of the study with the current literature.

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2. MULTIPLE-VALUED LOGIC ALGEBRA

Digital binary systems use just two logic symbols, “0” and “1” to represent all information. Since the real world is not binary, we cannot surely claim that using two values is an optimum choice. In 1921, Post [5] gave a definition of r-valued logic that was a generalization of the usual 2-valued logic. In 1970’s, circuit level realizations of r-valued logic become apparent in the literature as voltage mode ternary circuits.

For the last couple of decades multiple-valued logic circuits became more visible in the literature and in commercial products. These circuits have the potential advantage of reducing the number and complexity of interconnection wires because multiple-valued signals carry more information on a single line. As an example, consider the decimal number ‘255’, which can be represented as ‘11111111’ in binary logic and as ‘3333’ in quaternary logic. Designing the circuit as 4-valued rather than binary, at least decreases the number of digits to its half.

Multiple-valued circuits can be realized as voltage-mode or current-mode, depending on the operation and complexity of the circuit. On voltage-mode circuits, the information is transferred by voltage levels. Ternary circuits are better candidates for voltage-mode realization, especially for the circuits using dual supply voltages and signed digit arithmetic. Maximum allowable radix of the voltage-mode designs are determined by the supply voltage. As the technology developed, chip densities have increased and only very little power can be dissipated per cell to avoid the chip from overheating. That makes supply voltage levels critical in circuit designs. In addition, for portable electronic devices, battery life is directly related to power consumption, which makes low power design a very important criteria for analog and digital integrated circuits. Since power consumption of the circuit is related to the square of the supply voltage, reduction of the supply voltage is the first choice for reducing power consumption, leading into reducing dynamic range of the voltage-mode signal. As a result, we have limited radix at voltage-mode. Using transistors having variable threshold voltages can be thought as a solution for voltage mode designs but it is still limited with quaternary logic levels.

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On current-mode realizations of multiple-valued logic circuits, the information is transferred by current levels, that are integer multiples of a reference current. Current-mode circuits allow higher radix than voltage-Current-mode circuits, which makes them preferable to voltage-mode ones as we need to increase the system speed and the information content of the current carrying wires. The main advantage of the current-mode multi-valued circuits is the simplicity of the addition operation. This basic and most used operation of logic design can be performed simply by connecting signal lines into a single node, resulting in a reduced number of active devices in the circuit. (every single addition operation in binary logic design requires 20 transistors). In addition, currents can be copied, scaled and algebraically sign-changed with a simple current mirror. However, current-mode circuits have larger static power consumption and unlike binary circuits, they are not self-restoring. Cascaded stages will result a deviation from the predefined output levels, and it is necessary to restore the output to its original level.

2.1. Definitions for Multiple-Valued Algebra

An r-valued, n-variable function can be defined as 𝑓(𝑋), where X ={x x₀, ₁,...,xn−₁} and each x_i takes on values from the set R={0,1,...,r−1}. Then, the function is mapping

: n

f R →R, which means there arer(rn) possible different functions [65]. For example, if r=2 and n=2, there are 16 possible functions and if r=3 and n=2, then there are 19683 possible functions.

Consider an r-valued n-digit numberan−₁an−₂...a a₁ ₀. It represents the number

1 2 0 1 2 ... 0 n n n n a r − a r − a r − + − + + (2.1)

in decimal number system. Here, r=2 for binary, r=3 for ternary, and r=4 for the quaternary cases.

In this study, due to its potential advantages, current mode circuits are chosen for the realization of the multi-valued circuits. The reference current level, Ib, is chosen as 5µA and increases with its integer multiples as shown in Table 2.1.

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Table 2.1. Current levels of multi-valued current-mode signals.

Logic Level Current Level

0 0A

1 5µA

2 10µA

3 15µA

The indicated current levels can be deviate from their original values due to some variations in active element dimensions, power supplies, technology parameters, etc., and unlike binary voltage-mode circuits, the variation on the output signal is carried to the next stages. This deviation can be tolerated and output can be detected correctly for a range of value that is called noise margin [1, 66]. Including the existence of current deviations from their original values, logic levels can be defined as follows,

0, 2.5 1, 2.5 7.5 2, 7.5 12.5 3, 12.5 I A A I A l A I A A I µ µ µ µ µ µ <   _{≤ <}  =  _{≤ <}   _≤  (2.2)

where l is the logic level and I is the current. As it can be understood from the equation, the noise margin is ±Ib/2. Unlike voltage mode binary circuits, variations in the output current

carried over stages, which cause accumulated error. For this reason, output current level of multi-valued circuits need regeneration operation before the signal exceeds the noise margin, that is called level restoration, which is explained in detail in later chapters.

2.2. Basic Multi-Valued Circuit Elements

Choosing current-mode circuits in realization of multi-valued logic has some advantages as discussed before. In this section, brief description of mostly used current-mode basic circuit elements will be introduced.

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• Sum: The main advantage of current-mode implementation of multiple-valued circuits is its zero cost summation operation. Connecting current branches with a node simply performs an addition operation, y = x1 + x2 +…..+ xn, (algebraic sum) as shown in Figure 2.1.

Figure 2.1. Addition operation in current-mode MVL.

Addition operation in voltage mode binary circuits need an XOR and AND operator which has 20 transistors in total.

• Constant: Constant logic level determining the logic steps is generated by enhancement mode p-type or n-type transistors depending on whether sourcing or sinking action are desired. In this study, the reference current level is chosen as 5µA.

• Current mirror: Mirror circuits are used to produce the replicas of input currents. They can be designed as n-type or p-type as shown in Figure 2.2. These circuits are used to provide fan-out greater than one, because current-mode CMOS logic allows fan-out of only one. In addition, by rearranging transistor dimensions, any current value in the design can be multiplied by a constant k (called the scale factor), as shown in Figure 2.3 and their direction (sign) can be changed as shown in Figure 2.4

xn

x1

y ...

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Figure 2.2. n-type and p-type current mirrors. Iref I1 (W/L) k*(W/L) VDD Iref (W/L) k*(W/L) I1

Figure 2.3. Multiplying a current by a constant k.

VDD

I I

Figure 2.4. Current redirecting circuit.

• Switch: It is an n-type or p-type transistor. Gate terminal of the transistor is controlled by a voltage signal, and the current can flow when the switch is ON.

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2.3. CMOS Current-Mode Binary/MVL Encoding and Decoding

Multiple-valued logic has many theoretical advantages -its potential to increase the functional density of metal-limited digital integrated circuit layouts by reducing the number of signal interconnections required is the most promising one- but it is not widely used because MVL circuits do not provide overwhelmingly advantageous characteristics, in general. However, overall system characteristics may be improved using specific MVL circuits in specific applications.

Using the multiple-valued logic circuits as a part of a total design needs on-chip conversion from binary voltage signals to multiple-valued current-mode signals -encoding- and from multiple-valued current-mode signals to binary voltage signals -decoding- as shown in Figure 2.5. Encoder Binary OUT Binary IN r-valued current-mode circuits Decoder

Figure 2.5. Using MVL circuits in binary designed systems.

There are compact and accurate designs of encoder and decoder circuits using current comparator circuits. Current comparator [64], or current threshold detector, circuits are key components in current-mode multiple-valued logic design as shown in Figure 2.6.

The circuit introduced in Figure 2.6 is the simplest form of current-comparator circuits. Input diode-connected NMOS-PMOS transistor pair produces the threshold current. This reference current is mirrored to output as Ith, and input current is mirrored to

output as Iin. The output of the comparator circuit is at logical HIGH voltage (output node

has the same potential with power supply) when the input current is less than the threshold current and at logical LOW voltage (output node has the same voltage with the ground) when the input current is greater than the threshold current as shown in Equation 2.3. Applying the input current over PMOS transistor mirror, and threshold current over NMOS, produces the inverted version of output voltages, if needed.

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in th o in th High if I I V Low if I I <  =  _≥  (2.3)

I

in VDD

I

th Vo

Figure 2.6. Current comparator circuit.

Performance limitations of the current comparator will determine the threshold circuits’ ability to discriminate between different input current levels. A large gain is desired to provide a sharp comparator transition and greater noise margin.

Encoding operation for MVL signals is simply converting the voltage-mode binary signals to current-mode multiple-valued signals. An example for the encoder circuit can be found in [63] and shown in Figure 2.7. This circuit accepts the 2-bit binary input and produces a 1-digit quaternary output for quaternary conversion operation. For the n-bit input signal, the circuit can produce 2n levels output current. The diode connected NMOS-PMOS pair produces a base current and it is reflected to the output with the coefficient 2k where k= {0,1,…,n-1}. Binary input bits are applied to the gates of the NMOS transistors to enable the current contrubute to the output current, Iout. Choosing the number of logic levels of MVL circuit as a power of 2 makes encoding and decoding easier and systematic.

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VDD

I 2I

MSB LSB

Iout

Figure 2.7. Encoder circuit.

Once the binary signal encoded to its MVL counterpart and processed in a MVL circuit, it needs to be decoded again for the rest of the system. Decoding operation is based on current comparison. Multiple-valued input current compared with the (n-1) reference currents to produce log₂n binary voltage signals as shown in Figure 2.8. Output voltage levels of (n-1) comparator outputs are converted to a binary output using an appropriate combinational logic block.

I

in VDD MSB LSB B _ A+BC _ _____

A

B

C

0.5I 1.5I 2.5I 2I

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2.4. Multiple-Valued Operators

In addition to basic circuit elements explained in the previous section, we need to define multi-valued operators for the MVL circuit design and synthesis. Some of the operators are extensions of binary logic, and some of them are defined for multiple-valued logic. Definitions of some MVL operators, especially those useful for the rest of the study, are as follows:

Definition 2.1. The complement (negation, inversion) operator is defined as:

1

x = − −r x (2.4)

where x∈R. The operation can be simply realized by using a current mirror as shown in Figure 2.9, ensures the truth table given in Table 2.2.

Table 2.2. Truth table for complement operator.

x

0 1 2 3

x 3 2 1 0

x

x (r-1)

Figure 2.9. Complement operator.

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0 x ky if x ky z x ky otherwise − ≥  = Ξ _{= }  (2.5)

Truncated difference operator serves a basis for many other multiple-valued operators. Implementation of the circuit requires an n-type current mirror similar to those used in complement operation, except the inputs are applied as y and x respectively with the scale factor of k as shown in Figure 2.10.

y

z x

1 : k

Figure 2.10. Truncated difference operator.

Definition 2.3. The lower and upper threshold operators are main building blocks for

MVL circuits and can be defined as:

if : | 0 otherwise l z z x y th x y ≤  =   (2.6) z if : | 0 otherwise u z x y th x y ≥  =   (2.7)

where x,y,z∈R. Several implementations of the threshold literal circuits can be found in the literature. For the realization of the latter circuits in these study, circuits from [68] are chosen for their full current-mode, fast and reliable structures. Truth table for the threshold literal operations (assuming z=r-1=3) are given in Table 2.3 and the lower threshold circuit is given in Figure 2.11.

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In order to realize the upper threshold circuit, interchanging the x and y inputs of lower threshold circuit is enough.

Table 2.3. Truth table for lower and upper threshold operations.

l th th_u y x 0 1 2 3 y x 0 1 2 3 0 3 3 3 3 0 3 0 0 0 1 0 3 3 3 1 3 3 0 0 2 0 0 3 3 2 3 3 3 0 3 0 0 0 3 3 3 3 3 3 y x z th_l

Figure 2.11. Lower threshold circuit.

Definition 2.4. The window literal operator [12] is defined as:

_{1 if}

0 otherwise

a b _r _a _x _b

z= x =  − ≤ ≤

 (2.8)

Lower threshold and upper threshold circuits are special cases of window literal operation. In order to realize a lower threshold, we can set the value of a=0, and for an upper threshold realization b=r-1. Using these properties, window literal –literal, in short– circuit can be realized as cascading the lower threshold and upper threshold circuits respectively as shown in Figure 2.12.

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x x a-0.5

b+0.5 r-1

z

Figure 2.12. Window literal operator.

Definition 2.5. The cyclic operator takes the input value, and shifts it with the

specified amount of current. If the shift operation is performed as addition of the specified amount to the input value, then it is called clockwise cyclic operation. If the shift operation is performed as subtraction of the specified amount from the input value, then it is called counter-clockwise cyclic operation.

, if 1 , : , y x y x y r clockwise cyclic CWC x x y r otherwise → _{= } + + ≤ − + −  (2.9) , if 0 , C : , y x y x y

counter clockwise cyclic CWC x

x y r otherwise

←  − − ≥

=  _{− +}

 (2.10)

Truth tables for clockwise cycling and counter-clockwise cycling circuits are given in Table 2.4. Realization of the clockwise cyclic circuit from [69] is given in Figure 2.13.

Table 2.4. Truth tables of clockwise cyclic and counter clockwise cyclic operators.

CWC CCWC y x 0 1 2 3 y x 0 1 2 3 0 0 1 2 3 0 0 3 2 1 1 1 2 3 0 1 1 0 3 2 2 2 3 0 1 2 2 1 0 3 3 3 0 1 2 3 3 2 1 0

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y x r r-0.5 VDD xy

Figure 2.13. Clockwise cyclic operator.

For design simplicity, successor and predecessor operators can be defined as a special cases of CWC and CCWC operators for y=1.

: ( 1) mod

successor x₊ = x+ r (2.11)

: ( 1) mod

predecessor x₋ = x− r (2.12)

Definition 2.6. The min operator [5] takes the input values, and produces an output

that is equal to the minimum of the input values, as follows:

( , ) ( , ) .

min x y = AND x y = x y (2.13)

where x y, ∈R. The truth table of the min operator is given in Table 2.5.

There are various examples for the realization of the min circuit that can be found in the literature. An example can be found in [69] that needs only 4 transistors. The operation of the circuit is depending on truncated difference operation as follows:

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( ) ( ) z x x y y y x = Ξ Ξ = Ξ Ξ (2.14)

Table 2.5. Truth table for min operator.

y x 0 1 2 3 0 0 0 0 0 1 0 1 1 1 2 0 1 2 2 3 0 1 2 3

Realization of the min circuit is introduced in Figure 2.14. Performance of the circuit is quite well and the circuit is totally level independent, which is a desired property for multiple-valued logic designs. The main drawback of the circuit is it allows only two input variables. Whenever the number of input variables increases, the circuit needs to be cascaded which increases the transistor count, power consumption and delay considerably.

x y y

z

Figure 2.14. min circuit introduced in [69].

When we speak about large array of input values, Winner-Takes-All (WTA) and Loser-Takes-All (LTA) circuits are used for choosing the max/min of the input signals. Winner-take-all circuit is introduced by Lazzaro [47] with a primitive building block whose computation is continuous in time and no clock signal is needed. Several WTA and LTA circuits are developed and reported [48-52, 54, 56-59, 70] in the literature after

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Lazzaro’s primitive structure. They have increased speed and resolution. A detailed comparison of WTA circuits can be found in [53].

For the rest of the this study,LTA structured min circuit that has multi-input single-output [52] is used whenever the min operation is needed. Transistor-level circuit schematic is introduced in Figure 2.15.

x y

min(x,y,...) VDD

Ibias

Figure 2.15. Multi-input min circuit [52].

Definition 2.7. The max operator takes the input values, and produces an output that

is equal to the maximum of the input values.

( , ) ( , )

max x y = OR x y = x + y (2.15)

where x y, ∈R. Truth table of the max operator is given in Table 2.6.

There are various examples for the realization of the max circuit that can be found in the literature. An example can be found in [69]. The operation of the circuit depends on the truncated difference operation as follows:

( )

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Table 2.6. Truth table for max operator. y x 0 1 2 3 0 0 1 2 3 1 1 1 2 3 2 2 2 2 3 3 3 3 3 3

Realization of the circuit is introduced in Figure 2.16. With the appropriate selection of PMOS transistor dimensions, operation of the circuit can be totally level independent. The main drawback of the circuit is it allows only two input variables.

x y

z

VDD

Figure 2.16. max circuit introduced in [69].

When a large array of input values is desired, Winner-Takes-All (WTA) circuits are the best candidates to realize max circuits. In this study, a WTA structured max circuit chosen from [48] is used, as shown in Figure 2.17. It has a very compact structure. Every single increase in number of input variable needs three transistors only.

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VDD

x y

max(x,y,...)

. . .

Figure 2.17. Multi-input max circuit [48].

From the definitions stated above, min and max are two-element (or multi-input), others are unary (single input) operators. The operators obey Boolean algebra axioms with

2

r≥ . The min and max operators are commutative, associative, absorptive, and distributive [71].

Definition 2.8. A k-valued product term is given by

{0,1,.., } : ( ) k i i n P g x k ∈ =  (2.17)

where, g(xi) refers to a unary operator such as cyclic, literal, etc. and ‘’ refers to min operator over the unary operators.

Definition 2.9. A multiple-valued combinational function can be expressed in terms

of product as: 0 1 ( , ,..., _n) _j j R f x x x P ∈ =  (2.18)

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where, ‘_’ refers to max operator.

Under these given definitions, functional completeness of the multiple-valued algebra is discussed in the next session.

2.4.1. Functional Comleteness of Multiple-Valued Algebra

An r-valued algebra is said to be functionally complete if it is possible to describe any n-variable fuction as an expression made up of constants, variables and defined operations. In binary logic, there are a limited number of operators, it is relatively easy to define a useful functionally complete algebra. In a multiple-valued logic system, the number of possible functions increases with the double exponential expression, resulting in a rapid increase in the total number of operators.

Post [5] showed that a minimal or a complete MVL algebra can be formed from only one two-element operator and one unary operator, for example, min/max and complement or min/max and cyclic.

Consider the truth table of 4-valued, 2-variable function given in Table 2.7. Table 2.7. Truth table of a 4-valued, 2-variable example function.

x2 x1 0 1 2 3 0 0 0 0 2 1 1 1 1 2 2 1 1 3 2 3 3 3 3 3

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0 0 3 3 1 1 0 0 1 1 1 1 1 1 2 2 1 1 3 3 1 2 1 2 1 2 1 2 1 2 1 2 2 2 0 0 2 2 1 1 2 2 2 2 2 2 3 3 1 2 1 2 1 2 1 2 3 3 0 0 3 3 1 1 3 3 2 2 3 3 3 3 1 2 1 2 1 2 1 2 ( , ) 2. . 1. . 1. . 1. . 2. . 1. . 1. . . 2. . . . . . f x x x x x x x x x x x x x x x x x x x x x x x x x x x x = + + + + + + + + + + + + (2.19)

where, ‘.’ denotes the min operation and ‘+’ denotes the max operation. To express the equation in more readable form, ‘.’ sign can be dropped and ‘ j

i

x ’ notation can be used for the literal operation ‘j j

i

x ’. In order to minimize this huge expression, we can rewrite the truth table under the definition of some properties of literal circuits [72].

Property: Let a and b be constants such that a≤b and a b, ∈R. Then

1 2 ( 1 2) 2

i j i j j

a x⋅ + ⋅b x = ⋅a x +x + ⋅b x (2.20)

Using this property we can rewrite the function of Table 2.7 as Table 2.8. For clarity in reading, 0 values are not shown. The ‘X’ values in the table are don’t cares that are created by the help of the property given above. The ‘+’ sign denotes the max operation. The rest of the minimization is similar to the Karnaugh map minimization technique in binary logic.

Table 2.8. Rearranged truth table of the given example function. x2 x1 0 1 2 3 x2 x1 0 1 2 3 x2 x1 0 1 2 3 0 X 0 2 0 1 1 1 1 X

+

1 2

+

1 2 1 1 X X 2 X 2 2 3 3 X X X X 3 X X X X 3 3 3 3 3

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1 3 3 3 3 3 2 3 2 2

1 2 1 2 1 1 2

( , ) 1. 2.

f x x = x + x + x + x x (2.21) There are several studies in the literature about the minimization of multiple-valued circuits [12, 65, 73-74], but it is still hard to minimize complicated functions efficiently.

2.5. Statistical Mismatch Analysis

Mismatch is the process that causes time-independent random variations in physical quantities of identically designed devices. Mismatching is a limiting factor in general-purpose analog signal processing, but especially in multiplexed analog systems, digital-to-analog converters, reference sources, etc [75]. Characterization and simulation of MOS transistor mismatch is important. Mismatch models include two terms: (i) a size dependent and (ii) a distance dependent term. The distance dependent term can be compensated through layout techniques, and is consequently less critical for precise analog design [76].

2.5.1. MOS Transistor Mismatch Model

Although, there are studies in the literature [77] that claims alpha-power law model (ID~(VGS-VT)α) should be applied for the current technology with α 1.2, some others [78] claim that square-law model (α =2) is still accurate. Assuming that a transistor is operating in the saturation region, the drain current will be expressed as follows:

2 ( ) 2 D GS T I =β V −V (2.22) where n ox W C L

β µ

= (2.23) and

(

)

T TO SB V =V +γ φ+V − φ (2.24)

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GS

V and V_SB are the gate-to-source and gate-to-bulk potentials respectively, φ is the surface potential and γ is the body-bias parameter of a MOS transistor. Mismatch that can be observed between the parameters of a group of equally designed transistors is the result of several random processes which occur during every fabrication phase of the devices. Any variations in these parameters of two matched transistors would cause a difference in the currents of equally biased transistors. The physical causes for variations in these parameters are fixed oxide charges, depletion charges, edge roughness, variations in substrate doping, oxide thickness and mobility values. Variations in any parameter may have systematic and random causes. Topography of the layout and gradients in oxide thickness and wafer doping cause systematic variations in the parameters along a wafer and among different batches [79]. On the other hand, random, local variations in physical properties of the wafer cause mismatch between closely placed transistors. Non-uniform distribution of dopants in the substrate and fixed oxide charges are responsible for local zero-bias threshold voltage mismatches whereas variations in substrate doping is the only cause for γ mismatch. The mismatch in the current factor β is due to edge roughness and local mobility variations [76, 80-81]. A mathematical analysis for the matching of MOS transistors was carried out by several researchers. The mismatch in a parameter is modeled by a normal distribution with zero mean. Moreover, the variance of the distribution for mismatches in the zero-bias threshold voltage, substrate factor and current factor coefficient can be expressed as [76, 80],

(

)

2 2 TO 2 2 TO V TO V x A V S D WL σ ∆ = + (2.25)

( )

2 2 2 2 x A S D WL γ γ σ ∆ =γ + (2.26)

( )

2 2 2 2 2 2 2 2 2 2 2 2 2 ox n ox n x A W L C S D W L C WL β β σ β σ σ σ σ µ β µ ∆ = + + + = + (2.27) where , , , , , TO TO V V

A A_β A_γ S S_β and S_γ, are process related constants, W and L are the length and width of the transistors, and D_x is the spacing between the matched transistors.

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Hence, the output current can be expressed as a function of mismatches, and the variance can be calculated as;

2 2 2

2 2 2 2

out TO

out out out

I V TO I I I V γ β σ σ σ σ γ β ∆  ∂  ∂  ∂  =_ _ +_ _ +_ _ ∂∆ _∂∆ _ _∂∆ _   (2.28)

Using these definitions of mismatch and analysis result of previous studies [82], logic level of 5µA is found suitable for the rest of the study. Simulations of the circuits used in this study show us that choosing Ib=5µA allows us ±2.5µA error, that is enough for

keeping the current at the predefined logic level. As the reference current minimized, increasing the number of logic levels becomes harder, since the output needs to reach the restoration circuit before it exceeds the allowable noise margin.

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3. SEQUENTIAL MVL CIRCUITS

Discussion about logic circuits can be divided into two classes; combinational logic and seque ntial logic. Combinational logic has the property that the output of the circuit is related directly to its present input signals by some Boolean expressions at any time instant. This property also holds true for multiple-valued logic circuits. Operators defined in the previous chapter produce outputs at any instant of time that are entirely dependent to the inputs at that time and obey the rules of Post algebra.

For the sequential logic case, the outputs depend not just on the current values of the inputs, but also on the past values of the outputs. In other words, sequential logic circuits have memory in addition to their combinational parts as shown in Figure 3.1.

Combinational Circuit

Memory

Outputs Inputs

Figure 3.1. Block diagram of a seque ntial circuit.

The combinational circuit in the block diagram can be the circuits introduced in the previous chapter, or new circuits that can be defined specifically for the given function. For the memory part of the sequential design, we need multiple-valued storage elements that hold and feedback the outputs to the input. This memory may be a latch circuit.

There are two main types of sequential circuits, namely: asynchronous and synchronous. Whenever an external signal controls the timing of the circuit, it has been called synchronous (clocked). For the asynchronous case, the output changes as soon as the input changes.

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The memory elements used in clocked sequential circuits are called flops. A flip-flop is capable of storing 1-bit information for the binary case and 1-digit information for the multiple-valued case. Flip-flop circuits can hold their states as long as the power delivered until they are directed by an input clock signal to switch the states. The number of inputs they process and the relationship between the input and output signals determines the type of the circuit.

Flip-flops circuits can be realized using multiple-valued logic circuits. Huertas and Acha [14-15, 17] defined the next-state equations of T-cyclic, RS, and JK multistables. Studies about implementation of these flip-flops can be found in the literature but they are very limited. Some of these studies are made by fuzzy logic researchers. There are similarities between fuzzy logic and multiple-valued logic. In fuzzy logic, the output is not represented as true or false, instead a membership function used to indicate the level of truth. Fuzzy logic allows for set membership values between the range [0, 1]. Dividing the range [0, 1] into some number of values is fundamentally similar to multiple valued logic [62, 83].

In designing multiple-valued seque ntial logic circuits, it is important to have suitable, uncomplicated and inexpensive storage elements (memory cells).

3.1. Multiple-Valued Latch

In order to realize a multiple-valued seque ntial circuit, multiple-valued storage elements are needed. The core of these elements are latch circuits that are capable of storing 1-digit information at a time. There are several latch circuits in the literature, most of them are realized as ternary or quaternary voltage mode [43, 45-46]. When designing ternary circuits, it is reasonable to choose ternary voltage-mode latch circuit, especially with the dual supply voltage. For the quaternary case, as the technology shrinks the supply voltage, latch circuits tend to use FETs that have different threshold levels.

In this study, current-mode multiple-valued circuits used. In literature, the only current-mode multiple-valued latch circuit -to the best of our knowledge- is the one proposed by Current [44] as shown in Figure 3.2.

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Iin clk A B C clk B C A VDD Mn1 Mp1 Mp2 Mp3 Mn2 Mn3 __ Mpass1 Mpass2 Iout Mref1 Mref2 Irg

Figure 3.2. Current-mode CMOS quaternary latch circuit.

In this circuit, there are two phases of operation, namely SETUP (logically High clock signal) and HOLD (logically Low clock signal). When the clock signal ‘clk’ is high the diode connected input transistor receives the input current Iin, and in response generates a voltage VGS1 that that is coupled to the Mn1…Mn3 transistors through Mpass1 pass transistor. So, the input current is mirrored by the three NMOS transistors Mn1…Mn3. Mni -Mpi transistor pairs form the quantizer portion of the latch, composed of three current comparators. The current comparators’ thresholds are set to detect input currents of logical values of 1, 2, and 3 by adjusting the W/L ratios of three PMOS transistors Mp1…Mp3. Output of the each comparator circuit falls into logical LOW state whenever the input current exceeds the threshold of the comparator. In addition, output of each comparator circuit drives a standard CMOS inverter (voltage-mode binary output). The labeled inverter outputs drive pass transistors with the same label. The pass transistors let the appropriate quantity of current to the feedback summing node to form the regenerated current Irg when activated. This regenerated circuit mirrored to the output to form the output current Iout. When the clock signal ‘clk’ is high, the latch circuit performs the HOLD operation and the circuit isolated from the input current Iin. The high clk signal turns on the Mpass2 transistor and connects the generated current to the quantizer output. Since the quantizer and Irg are in a positive feedback loop, the regenerated current, Irg, and the output current, Iout, remain stable at the value of the previous input current.

Since the circuit performs both latching and restoring operation, positive feedback does not cause any oscillation in the output current. The only problem with this circuit is, it

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needs ‘r-1’ quantizing transistor pairs and ‘r-1’ regenerating transistors. As the radix increase in the design, this increases the number of active elements dramatically. On the other hand, since every single quantizer set to a predefined current level, the power consumption of the circuit increasing significantly as the radix increases.

Due to the these drawbacks of Current’s circuit [44], a new latch circuit is proposed and used in this study as shown in Figure 3.3.This circuit is based on Morgul and Temel’s level restoration circuit [84], The level restoration sets the current level to a predefined logic level. The restoration circuit is obtained by cascading restoration stages of Figure 3.3.

r

_i -0.5

r

_i

x

_i-1

x

_i-1

x

i

<x >

_i

Figure 3.3. Restoration stage. The number of restoration stages is calculated by

2

#of cascaded stages log= r−1 (3.1)

i.e., three stages are necessary for 8-level design. Assume that ‘xi’ is the input current of ith stage and ‘< xi >’ is the restored value of that stage. Every single stage performs the upper threshold operation to calculate the restored output as follows:

0.5 r_i i _r i x x − < >= (3.2) where,

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/ 2i i

r =r (3.3)

Then, the following quantities are used to obtain the intermediate restored value:

1 1 1 2 2 1 2 2 1 [mod( / 2)], ( ) [mod( / 2 )], ( ) . . . [mod( / 2 )]k k k x x r x x x x x r x x x x x ₋ r < >= = − < > < >= = − < > < >= (3.4)

and total restored current can be found by summing up the individual restored outputs:

2 log 1 1 r i i x x − = < >=

∑

< > (3.5)

Holding and storing operation in current-mode is not as easy as in the voltage-mode operation. The main idea of current-mode latch circuit is obtaining the current in SETUP mode and storing as long as the HOLD signal is available. Storing operation needs a continuous feedback of the output signal to the input, which feeds the error back too. In order to get rid of feeding the error back, a restoration circuit can be used. However, using a latch circuit that has its own restoration property is even better.

Adding two pass transistors stimulated by clk and clk signals turns this level restoration circuit into a latch circuit with restoration property. Logical HIGH clock signal implies the SETUP mode, which enables the input pass transistor and the input current is regenerated at the output. Logical LOW clock signal implies the HOLD cycle, which enables the pass transistor at the feedback path and allows the output behave as an input signal. Since every input signal is regenerated, the output error is not accumulated. Input, latched output and clock signal waveforms of the simulated latch circuit are shown in Figure 3.4.

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Iin=X clk VDD VDD Iout Ib clk __ 0.5Ib 2Ib 1.5Ib <x> 4Ib 3.5Ib <x1> <x2> <x3> X X1 X2

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Figure 3.5. Input, output and clock signal waveforms of simulated 8-level latch circuit.

3.2. Multiple-Valued Flip-flops

Flip-flops are circuits that have two stable states (in binary logic) and can be used to store state information. Output of flip-flop circuits depend on their input(s) with some equation. In multiple-valued logic, input-output equations are complicated.

3.2.1. RS-Type Multistable

The set-reset flip-flop is the basic flip-flop structure in the binary logic. It has two inputs, namely Reset (R) and the Set (S). The characteristic equation for the binary flip-flop is as follows:

1

n

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and R=S=‘logic 1’ state is undefined and usually avoided. Similar to the binary reset-set (RS) type flip-flop, multiple-valued RS flip-flops have undefined transition states. The next-state equation of a multiple-valued RS-type flip-flop is given as follows [17]:

1 1 1 1 1 1 ( ) r i r i r i r n n i Q i S R Q − − − − + = =

∑

⋅ + ⋅ (3.7)

where S and R are set and reset inputs respectively and Qn indicates the present-state, Qn+1 is the next-state. The general transition table for r=4 is shown in Table 3.1.

Table 3.1. General transition table of R-S type multistable.

RS Qn 00 01 02 03 10 11 12 13 20 21 22 23 30 31 32 33 0 0 - - - 0 1 - - 0 1 2 - 0 1 2 3 1 0 - - - 1 1 - - 1 1 2 - 1 1 2 3 2 0 - - - 1 1 - - 2 2 2 - 2 2 2 3 3 0 - - - 1 1 - - 2 2 2 - 3 3 3 3 3.2.2. D-type Multistable

In order to eliminate the undesired condition of indeterminate state in the binary RS flip-flop, input is applied directly to S input and its compliment is applied to the R input. Operation of the D-type multiple-valued flip-flop is same as the binary case. The next-state equation defined in [16] is given as follows:

1

n

Q₊ =D (3.8)

where D is the flip-flop input and it is valid for the binary case too. General transition table of the D-type multiple-valued flip-flop is shown in Table 3.2.

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Table 3.2. General transition table of D- type multistable. D Qn 0 1 2 . . . r-2 r-1 0 0 1 2 . . . r-2 r-1 1 0 1 2 . . . r-2 r-1 2 0 1 2 . . . r-2 r-1 . . . . . . . . . . . . . . . . . . r-2 0 1 2 . . . r-2 r-1 r-1 0 1 2 . . . r-2 r-1 3.2.3. JK-Type Multistable

The JK flip-flop is a refinement of the RS flip-flop in that the undefined case of the RS flip-flop is defined in JK. The J and K inputs behave like S and R inputs. The operation of the flip-flop in binary case is defined as:

1 ( )( )

n n n n n

Q + = J+Q K+Q =JQ +KQ (3.9)

Since xx =0equation does not hold true for the multiple-valued case. The operation of the JK-type multiple-valued flip-flop [13-14] is represented by the next-state equation as follows:

1

n n n

Q + = ⋅J Q + ⋅K Q + ⋅J K (3.10)

where J and K are inputs and Qn is output. General transition table for r = 4 is shown in Table 3.3.

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Table 3.3. General transition table of J-K type multistable. JK Qn 00 01 02 03 10 11 12 13 20 21 22 23 30 31 32 33 0 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 1 1 1 1 0 1 1 1 1 2 2 2 2 3 2 2 2 2 2 2 1 0 2 2 1 1 2 2 1 1 3 2 1 1 3 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3.2.4. T-Cyclic Multistable

Binary T-type flip-flop is the single-input version of the binary JK flip-flop. This definition does not apply for the multiple-valued case. The T-cyclic multistable operation is defined by the next-state equation [15]:

1

T

n n

Q + =Q → (3.11)

where the clockwise cyclic operation defined in Equation (2.7) is employed as:

( mod )

T

n n

Q→ =Q +T R (3.12)

Here, Qn indicates the present-state where Qn+1 is the next-state. In addition, T is toggle input value and R is radix. General transition table of the T-cyclic multiple-valued flip-flop is shown in Table 3.4.

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Table 3.4. General transition table of T-cyclic type multistable. T Qn 0 1 2 . . . r-2 r-1 0 0 1 2 . . . r-2 r-1 1 1 2 3 . . . r-1 0 2 2 3 4 . . . 0 1 . . . . . . . . . . . . . . . . . . r-2 r-2 r-1 0 . . . r-4 r-3 r-1 r-1 0 1 . . . r-1 r-2

CURRENT-MODE CMOS SEQUENTIAL MULTIPLE-VALUED LOGIC CIRCUITS

ACKNOWLEDGEMENTS

ABSTRACT

CURRENT-MODE CMOS SEQUENTIAL MULTIPLE-VALUED

LOGIC CIRCUITS

ÖZET

AKIM-MODLU CMOS ARDI

Ş

IL ÇOK

DEĞERLİ

MANTIK

DEVRELER

İ

TABLE OF CONTENTS

LIST OF FIGURES

LIST OF TABLES

LIST OF SYMBOLS

.

LIST OF ACRONYMS/ABBREVIATIONS

1. INTRODUCTION

2. MULTIPLE-VALUED LOGIC ALGEBRA

I

I

I

A

B

C

x

. . .

+

+

β µ

(

)

(

)

( )

( )

( )

( )

( )

( )

3. SEQUENTIAL MVL CIRCUITS

r

r

x

x

x

<x >

∑

∑