Design and Analysis of On-Chip Router for Network on Chip

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International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459, Volume 2, Issue 1, January 2012)

143

Design and Analysis of On-Chip Router for Network on Chip

1

Anuprita.S. Kale,

2

Prof. M.A.Gaikwad

1

M.Tech Scholar, Electronics Department,Bapurao Deshmukh college of engineering, Wardha M. S.India

2_{Professor, Electronics Department,Bapurao Deshmukh college of engineering, Wardha M. S.India}

1_{[email protected]}

2_{[email protected]}

Abstract- Continuous scaling of CMOS technology makes it possible to integrate a large number of heterogeneous devices that need to communicate efficiently on a single chip. For this efficient routers are needed to takes place communication between these devices. This paper gives the design of on-chip routers based on optimizing power consumption and chip area. Proposed architecture of on-chip router in this paper give the results in which power consumption is reduced and silicon area is also minimize.

Index Terms- Arbiter, Network on chip (NOC), On chip Router, FIFO.

I. INTRODUCTION

1.1 Network on chip

A variety of interconnection schemes are currently in use, including crossbar, buses and NOCs. Of these, later two are dominant in research community. However buses suffers from poor scalability because as the number of processing elements increases, performance degrades dramatically. Hence they are not considered where processing elements are more. To overcome this limitation

attention has shifted to packet-based on-chip

communication networks, known as Network-On-Chip (NOC).

PE – Processing Element R - Router NI – Network Interface

Fig:1 Typical NOC Architecture

A typical NoC consists of computational processing elements (PEs), network interfaces (NIs), and routers. The latter two comprise the communication architecture. The NI is used to packetize data before using the router backbone to traverse the NoC. Each PE is attached to an NI which connects the PE to a local router. When a packet was sent from a source PE to a destination PE, the packet is forwarded hop by hop on the network via the decision made by each router. For each router, the packet is first received and stored at an input buffer. Then the control logics in the router are responsible to make routing decision and channel arbitration. Finally, the granted packet will traverse through a crossbar to the next router, and the process repeats until the packet arrives at its destination.

1.2 On-Chip Router

The heart of an on-chip network is the router, which undertakes crucial task of co-ordinating the data flow. The router operation revolves around two fundamental regimes: (a) the datapath and (b) the associated control logic. The datapath consist of number of input and output channels to facilitated packet switching and traversal. Generally 5 input X 5 output router is used. Out of five ports four ports are in cardinal direction (North, South, East, Waste) and one port is attached to it’s local processing element.

Like in any other network, router is the most important component for the design of communication back-bone of a NoC system. In a packet switched network, the functionality of the router is to forward an incoming packet to the destination resource if it is directly connected to it, or to forward the packet to another router connected to it. It is very important that design of a NoC router should be as simple as possible because implementation cost increases with an increase in the design complexity of a router.

II. RELATED WORK

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They get upto 94% of throughput but power consumption is increased by the factor of 1.28. Our approach may give the reduced power consumption.

A. Louri and J. Wang et. al [2] illustrates the impact of repeater insertion on inter-router links with adaptive control and eliminating some of the buffers in the router. Their approach saves appreciable amount of power and area without significant degradation in the throughput and latency. But there is still some scope to increase the buffer utilization inside the router.

Ying-Cherng Lan, Shih-Hsin Lo, Yueh-Chi Lin and Yu-Hen Hu et. al [3] addresses the buffer utilization by making the channels bidirectional and shows significant improvement in system performance. But in this case, each channel controller will have two additional tasks: dynamically configuring the channel direction and to allocate the channel to one of the routers, sharing the channel. Also, there is a 40% area overhead over the typical NoC router architecture due to double crossbar design and control logic.

Neishabouri et. al [4] proposes the router architecture with Reliability Aware Virtual Router. In this architecture they allocate more memory to the busy channels and less to the idle channels. This dynamic allocation of storage shows 7.1% and 3.1% latency decrease under uniform and transpose traffic patterns respectively at the expense of complex memory control logic. Though this solution is latency efficient but not area and power efficient.

III. PACKET FORMAT

Packet format used while designing the on-chip router is shown in figure 2. 160 bit packet is used. Out of 160 bits, first three bits are the destination address and next three bits are source address. Remaining 154 bits are the data bits.

IV. PROPOSED ROUTER ARCHITECTURE

Like in any other network, router is the most important component for the design of communication back-bone of a NoC system. In a packet switched network, the functionality of the router is to forward an incoming packet to the destination resource if it is directly connected to it, or to forward the packet to another router connected to it.

It is very important that design of a NoC router should be as simple as possible because implementation cost increases with an increase in the design complexity of a router.

The design of router mainly consist of three parts:

1. FIFO

2. Arbiter 3. Crossbar

Arbiter

FIFO Buffers Crossbar

Write

Read

So S1 S2 S3 S4

input port a

input port b

input port c

input port d

input port e

output port a

output port b

output port c

output port d

output port e

Fig.2: 5 Input 5 Output port Unidirectional On-Chip

Router

A. FIFO Buffer

Buffering is very essential in NoC for flow control and congestion control. Deciding proper size of buffer is the key issue for getting optimal performance. In this design the buffer of depth four is used to provide input buffering. The length of buffer is equal to the packet size. Since the depth of buffer is four, minimum four clock signals are required for first packet to come out of buffer.

B. Arbiter

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Supposing in a given period of time, there was many input ports request the same output or resource, the arbiter is in charge of processing the priorities among many different request inputs. The arbiter will release the output port which is connected to the crossbar once the last packet has finished transmission. So that other waiting packets could use the output by the arbitration ofarbiter.

A round-robin arbiter operates on the principle that a request which was just served should have the lowest priority on the next round of arbitration. Depending upon the control logic arbiter generate select lines for mux based crossbar and read or write signal for FIFO buffers.

C. Crossbar

A crossbar switch (also known as cross-point switch, crosspoint switch, or matrix switch) is a switch connecting multiple inputs to multiple outputs in a matrix manner. The design of crossbar switch has 5 inputs and 5 outputs. According to the select lines generated by arbiter, crossbar establishes the connections between input port and output port.

Table 1- Addresses assigned for input port and output port

Input Ports Address bits Output Ports Address bits

Port a 000 Port a 000

Port b 001 Port b 001

Port c 010 Port c 010

Port d 011 Port d 011

Port e 100 Port e 100

Table 1 gives the addresses assigned for input port and output port. Input port address is nothing but a source address and output port address is destination adderss.

V. SIMULATION RESULT

Simulation refers to the verification of a design, its function and performance. It is process of applying stimuli to a model over time and producing corresponding responses from a model. Round robin algorithm assigns priority to inputs and according to that we get the output. If two or more packets want to deliver on the same destination port then round robin arbitration stars and packets on the port which has highest priority is delivered to destination first.

Consider the packets to input ports as below (In hexadecimal)

Port a

111111101 2222222222 3333333333 4444444444 Port b

5555555508 6666666666 7777777777 8888888888 Port c

9999999914 AAAAAAAAAA BBBBBBBBBB CCCCCCCCCC Port d

DDDDDDDIC EEEEEEEEEE FFFFFFFFFF EEEEEEEEEE Port e

CCCCCCCC24 DDDDDDDDDD CCCCCCCCCC DDDDDDDDDD

160 bit packet is divided into four flits of 40 bits. First six bits of flit 1 consist source and destination address. With reference to above considered packets, destination address of each port is as given in table 2.

Table 2

Port First six bits of packet

Source address

destination address

Port a 01 H

(00000001)

000 001

Port b 08 H

(00001000)

001 000

Port c 14 H

(00010100)

010 100

Port d 1C H

(00011100)

011 100

Port e 24 H

(00100100)

100 100

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Fig.3.1 Output Waveform of on-chip router

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International Journal of Emerging Technology and Advanced Engineering

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Fig.3.3 Output Waveform of on-chip router (cont.)

VI.

CONCLUSION

In the current silicon era, NoC is not power and area efficient although it has higher throughput. Enhancement in the utilization of idle resources instead of inserting new ones can make the NoC an ideal solution for current applications. The proposed architecture of router consumes 7 mW of static power even though the packet size is 160 bit.

References

[1] V.Soteriou, R.S. Ramanujam, B. Lin, Li-Shiuan Peh. A High-Throughput Distributed Shared-Buffer NoC Router. IEEE Computer Architecture Letters, vol. 8, no. 1, pp. 21-24, Jan.-June 2009, doi:10.1109/LCA. 2009.5.

[2] A. Louri, J. Wang, Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs).”

[3] A. Kodi, A. Louri, J. Wang. Design of energy-efficientnchannel buffers with router bypassing for network-onchips (NoCs). Proceedings of International Symposium on Quality of Electronic Design (ISQED), pp.826-832, March 2009.