Chapter7-Instruction Sets.ppt

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Computer Organization

and Architecture

Chapter 7

Instruction Sets

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What is an instruction set?

►The complete collection of instructions The complete collection of instructions

that are understood by a CPU

►Machine CodeMachine Code ►BinaryBinary

(Usually represented by assembly codes)

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Instruction Representation

►In machine code each instruction has a In machine code each instruction has a

unique bit pattern

►For human consumption, a symbolic For human consumption, a symbolic

representation is used

 e.g. ADD, SUB, LOAD_{e.g. ADD, SUB, LOAD}

►Operands can also be represented in this Operands can also be represented in this

way

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High Level Language

Instruction Representation

Compiler

Assembly Language

Assembler

Machine Language

Interpreter

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Instruction Cycle

(refer to chapter 4)(refer to chapter 4)

Fetch Instruction Decode Instruction

Fetch Operand Execute at ALU

Store Result Next

Instruction Fetch instruction from program Memory

Determine required actions and instruction size

Locate and obtain operand data

Compute result, value or status

Save result in memory

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Instruction Types

►Data processingData processing

►Data storage (main memory)Data storage (main memory)

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Design Decisions

►Instruction formatsInstruction formats

 Length of op code field_{Length of op code field}

 Number of addresses_{Number of addresses}

►Operation selectionOperation selection  _{How many ops?}_{How many ops?}

 What can they do?_{What can they do?}

 How complex are they?_{How complex are they?}

►Data types and sizeData types and size

Fetch Instruction Decode Instruction

Fetch Operand Execute at ALU

Store Result Next

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Design Decisions

Fetch Instruction Decode Instruction Fetch Operand Execute at ALU

Store Result Next

Instruction

► Location of operands and resultLocation of operands and result

 Number of CPU registers _{Number of CPU registers}

available

 Which operations can be _{Which operations can be}

performed on which registers?

 which can or cannot be in _{which can or cannot be in}

memory?

► Addressing modesAddressing modes ► Next instructionNext instruction

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Major choices in the type of

internal storage in the CPU

► a stack a stack (the operands are implicitly on (the operands are implicitly on

top of the stack)

►an accumulatoran accumulator (one operand is (one operand is

implicitly the accumulator)

►a set of registersa set of registers (all operands are (all operands are

explicit either registers or memory

locations)

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The code segment C = A + B how it would appear on the classes of instruction sets

Stack Accumulator Register

PUSH A Load A Load R1,A PUSH B ADD B ADD R1,B ADD Store C Store C,R1 POP C

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Primary advantages and disadvantages of each class of machine

Machine

Type Advantages Disadvantages

Stack

Simple model of

expression evaluation. Good code density.

A stack can't be randomly

accessed. It makes it difficult to generate efficient code.

Accumulator

Minimizes internal state of machine. Short

instructions

Since accumulator is only temporary storage, memory traffic is highest.

Register Most general model for code generation

All operands must be named, leading to longer instructions.

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Types of Operand

►AddressesAddresses

►NumbersNumbers

 Integer/floating point_{Integer/floating point}

►CharactersCharacters  ASCII etc._{ASCII etc.}

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Specific Data Types

► General - arbitrary binary contentsGeneral - arbitrary binary contents ► Integer - single binary valueInteger - single binary value

► Ordinal - unsigned integerOrdinal - unsigned integer

► Unpacked BCD - One digit per byteUnpacked BCD - One digit per byte ► Packed BCD - 2 BCD digits per bytePacked BCD - 2 BCD digits per byte

► Near Pointer - 32 bit offset within segmentNear Pointer - 32 bit offset within segment ► Bit fieldBit field

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Data Transfer

►SpecifySpecify  Source_Source

 Destination_Destination

 Amount of data_{Amount of data}

►May be different instructions for different May be different instructions for different

movements

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Instruction Fetch Cycle (Steps 1 and 2)

► The CPU presents the The CPU presents the

value of the program

counter (PC) on the

address bus

► The CPU then fetches The CPU then fetches

the instruction from

main memory via the

data bus into the

Instruction Register (IR)

CU

Step 1

Step 2 Decode Instruction

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Execute Cycle (Steps 3 and 4)

► Read the effective address” Read the effective address”

from memory if the

instruction has an indirect

address address T1 T2 ALU CC D0 D6 D1 CU IR D7 A0 TP A1 PC SP 1 CU

Step 3 Operand Fetch

Step 4 Execute" the instruction

► From the instruction register, From the instruction register,

the data forming the instruction

is decoded by the control unit

► pass the decoded information as a sequence of control signals to the pass the decoded information as a sequence of control signals to the

function units to perform the actions required by the instruction

► Then pass them to the Arithmetic logic unit (ALU) for processingThen pass them to the Arithmetic logic unit (ALU) for processing ► write the result back to a register write the result back to a register

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Step 5. Store Result

►"Store" in memory any results generated by "Store" in memory any results generated by

the operation or send the results to an

output device

►Based on the condition feedback from the Based on the condition feedback from the

ALU, the PC is either incremented to

address the next instruction or updated to a

different address where the next instruction

will be fetched

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Two different competing

philosophies in designing modern

computer architecture

►complex instruction set computercomplex instruction set computer

(

(CISC_CISC)₎

►reduced instruction set computerreduced instruction set computer

(

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CISC

► A A complex instruction set computercomplex instruction set computer ( (CISCCISC) is ) is a microprocessor instruction set architecture (ISA)

a microprocessor instruction set architecture (ISA)

in which each instruction can execute several

low-level operations, such as a load from memory, an

level operations, such as a load from memory, an

arithmetic operation, and a memory store, all in a

single instruction

► Examples of CISC processors are the CDC 6600, Examples of CISC processors are the CDC 6600, System/360, VAX, PDP-11, Motorola 68000 family,

System/360, VAX, PDP-11, Motorola 68000 family,

and Intel and AMD x86 CPUs

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CISC

► requires the use of microcode to decode the requires the use of microcode to decode the (macro) instructions

(macro) instructions

► primarily motivated by a desire to reduce the

"semantic gap" between the machine language of the processor and the high-level languages in

which people were programming (Work well with simpler compiler)

► instruction set typically includes many instructions

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CISC

►many very complex instructions never or

seldom used, but they make the control unit extremely complex and thus have a high

control unit delay.

►Richer instruction set, some simple, some

very complex

►Instructions generally take more than 1

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RISC

►reduced instruction set computerreduced instruction set computer, or , or

RISC

RISC, is a microprocessor CPU design _{, is a microprocessor CPU design}

philosophy that favors a simpler set of

instructions that all take about the same

amount of time to execute

►most common RISC microprocessors are most common RISC microprocessors are

AVR, PIC, ARM, DEC Alpha, PA-RISC,

SPARC, MIPS, and Power Architecture

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RISC

►design philosophies behind RISC chip are

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RISC

►Simple primitive instructions and addressing

modes

►Instructions execute in one clock cycle

►simpler processor pipeline

►Uniformed length instructions and fixed

instruction format

►Instructions interface with memory via fixed

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RISC

►Hardwired control

►Complexity pushed to the compiler

►Large number of registers

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Who wins???

►RISC processors gain a reputation for high

performance

►nowadays, the difference between RISC and

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Bottom Line

►What counts in a real world is always how

fast a chip can execute the instructions it is given; and

►how well it runs existing software.

►Making a processor successful is more than

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“ The biggest threat for CISC and RISC might not be each other, but a new technology

called EPIC (Explicitly Parallel Instruction Computing)”

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References

► William Stallings. Computer Architecture and William Stallings. Computer Architecture and Organization, 2000

Organization, 2000

► Miles Morducca and Vincent Heuring. Principles Miles Morducca and Vincent Heuring. Principles of Computer Architecture, 1999

of Computer Architecture, 1999

► Hamacher, V. C., Vranesic, Z.G. and Zaky, S.G., Hamacher, V. C., Vranesic, Z.G. and Zaky, S.G., Computer Organization, 4th Ed.

Computer Organization, 4th Ed., McGraw-Hill, _{, McGraw-Hill,}

1996.

► Yi Gao, Shilang Tang, Zhongli Ding. Comparison