Arithmetic circuit

(1)

Arithmetic circuits



Binary addition



Binary Subtraction



Unsigned binary numbers



Sign-magnitude numbers



2’S Complement representation



2’S Complement arithmetic

(2)

Powers of 2

Powers of 2 20

21 22 23 24 25 26 27 28 29 210 211 212 213 214 215

Decimal Equivalent 1

2 4 8 16 32 64 128

256 512 1,024 2,048 4,096 8,192 16,384 32,768

Abbreviation

(3)

Decimal-Binary Equivalences

Decimal 1 3 7 15 31 63 127 255 511 1,023 2,047 4,095 8,191 16,383 32,767 65,535 Binary 1 11 111 1111 1 1111 11 1111 111 1111 1111 1111 1 1111 1111 11 1111 1111 111 1111 1111 1111 1111 1111 1 1111 1111 1111 11 1111 1111 1111 111 1111 1111 1111 1111 1111 1111 1111

(4)

Binary addition

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 10 = 0 + carry of 1 into next position

1 + 1 + 1 = 11 = 1 + carry of 1 into next position

A B SUM CO

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

HALF

ADDER

A B

SUM CO

Carry-Out =

SUM =

(AB)

(5)

Binary addition

Carry-Out =

SUM =

1-bit 8 Strings Full Adder with Carry-In and Carry-Out

CI A B SUM CO

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

FULL

ADDER

A B

SUM CO CI

(A B)CI + (A B)CI + +

(6)

1-bit 8 Strings Full Adder with Carry-In and Carry-Out

SUM =

FULL

ADDER

A B

SUM CO CI

(A B)CI + (A B)CI + +

(7)

(8)

Binary Subtraction

0 - 0 = 0

1 - 0 = 1

1 - 1 = 0

0 - 1 = 1 ต ้องยืมจากหลักที่สูงกว่า

มา 1

A B SUB BO

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

HALF

Subtractor

A B

SUB BO

Borrow-Out =

(9)

Binary Subtraction

Borrow-Out =

SUB =

1-bit 8 Strings Full Subtractor with Borrow-In and Borrow -Out

BI A B SUB BO

0 0 0 0 0

0 0 1 1 1

0 1 0 1 0

0 1 1 0 0

1 0 0 1 1

1 0 1 0 1

1 1 0 0 0

1 1 1 1 1

FULL

Subtractor

A B

(10)

REPRESENTING

UN

SIGNED NUMBERS

(

(Absolute valueAbsolute value))

0 0 0 0 0 0 0 0

A₇ A₆ A₅ A₄ A₃ A₂ A₁ A₀

=00H

1 1 1 1 1 1 1 1

B₇ B₆ B₅ B₄ B₃ B₂ B₁ B₀

(11)

REPRESENTING SIGNED NUMBERS

in

in sign-magnitudesign-magnitude form. form.

0 0 1 1 0 1 0 0

A₇ A₆ A₅ A₄ A₃ A₂ A₁ A₀

=+52

₁₀

SIGN BIT Magnitude = 5210

1 0 1 1 0 1 0 0

B₇ B₆ B₅ B₄ B₃ B₂ B₁ B₀

=-52

₁₀

SIGN BIT

(12)

REPRESENTING SIGNED NUMBERS

in the

in the 22’’ S-complement S-complement system. system.

0 0 1 0 1 1 0 1

A₇ A₆ A₅ A₄ A₃ A₂ A₁ A₀

=+45

₁₀

SIGN BIT True binary

1 1 0 1 0 0 1 1

B₇ B₆ B₅ B₄ B₃ B₂ B₁ B₀

=-45

₁₀

SIGN BIT

(13)

Range of Sign-Magnitude Numbers

0 0 0 0 0 0 0 1

A₇ A₆ A₅ A₄ A₃ A₂ A₁ A₀

=+1

₁₀

SIGN BIT

0 1 1 1 1 1 1 1

B₇ B₆ B₅ B₄ B₃ B₂ B₁ B₀

=+127

₁₀

1 0 0 0 0 0 0 1

A₇ A₆ A₅ A₄ A₃ A₂ A₁ A₀

=-127

₁₀

1 1 1 1 1 1 1 1

B₇ B₆ B₅ B₄ B₃ B₂ B₁ B₀

(14)

Range of Sign-Magnitude Numbers

0 0 0 0 0 0 0 1

A₇ A₆ A₅ A₄ A₃ A₂ A₁ A₀

=+1

₁₀

SIGN BIT

0 1 1 1 1 1 1 1

B₇ B₆ B₅ B₄ B₃ B₂ B₁ B₀

=+127

₁₀

1 0 0 0 0 0 0 1

A₇ A₆ A₅ A₄ A₃ A₂ A₁ A₀

=-127

₁₀

1 1 1 1 1 1 1 1

B₇ B₆ B₅ B₄ B₃ B₂ B₁ B₀

(15)

การคอมพลีเมนต์เลขฐาน

สอง

แบ่งออกเป็น



คอมพลีเมนต์

1 (1’s complement)



2 (2’s complement)



การคอมพลีเมนต์เลขฐานสองนี้นำาไปใช ้เกี่ยวกับ

การคำานวณทางไมโครคอมพิวเตอร์มาก

เพราะ

ว่าจะใช ้ในลักษณะการลบด ้วยวิธีการบวกด ้วย



สรุป

การลบด ้วยการบวกด ้วยคอมพลีเมนต์นั้นจะ

(16)

การคอมพลีเมนต์เลขฐาน

สอง

X

₃

X

₂

X

₁

X

₀

=

1000

1’s complement

X

₃

X

₂

X

₁

X

₀

=

0111

2’s complement

2’s complement = 1’s complement + 1

X

₃

X

₃

X

₂

X

₂

X

₁

X

₁

X

₀

(17)

Positive and Negative Numbers

-8 -7 -6 -5 -4 -3 -2 -1 0 +1 +2 +3 +4 +5 +6 +7

1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111

Magnitude Positive Negative 1

2 3 4 5 6 7 8

0001 0010 0011 0100 0101 0110 0111

(18)

2

’

S-complement representation summary



Positive numbers always have a sign bit of 0, and

negative numbers always have a sign bit of 1.



Positive numbers are stored in sign-magnitude

form.



Negative numbers are stored as 2’s complements.



Taking the 2’s complement is equivalent to a sign

(19)

Example :

Binary contents Hexadecimal contents Decimal contents

0001 0100 ____ ____ ____ ____ ____ ____ 1001 1110 ____ ____ ____ ____ ____ ____ ___ ___ ___ ___

14H DDH ___H

BDH ___H

70H ___H

6EH _____H

+20 ___ +47

___ ___ ___ -125

___ -19,750

1101 1101 -35

0010 1111 2F 1011 1101 -67

9E -98

0111 0000 +112

1000 0011 83

0110 1110 110

(20)

CASE 4 Both negative.

-43 -78

ADDITION

CASE 1 Both positive.

+83 +16

2’s complement arithmetic

0101 0011 0001 0000

83 0101 0011

+16 +0001 0000

99 0110 0011

CASE 2 Positive and

smaller negative.

+125 -68

0111 1101 1011 1100

125 0111 1101

+(-68) +1011 1100

57 1 0011 1001

CASE 3 Positive and larger

negative.

+37 -115

37 0010 0101

+(-115) +1000 1101

1101 0101 1011 0010

-43 1101 0101

+(-78) +1011 0010

(21)

SUBTRACTION

CASE 1 Both positive.

+83

+16

2’s complement arithmetic

0101 0011 0001 0000

CASE 2 Positive and

smaller negative.

+68 -27

83 0101 0011

+(-16) +1111 0000

67 1 0100 0011

0100 0100 1110 0101

68 0100 0100

+(+27) +0001 1011

95 0101 1111

CASE 3 Positive and larger

negative.

+14 -108

14 0000 1110

+(+108) +0110 1100

1101 0101 1011 0010

CASE 4 Both negative.

-43 -78

-43 1101 0101

+(+78) +0100 1110

(22)

S8 S7 S6 S5 S4 S3 S2 S1 S0

B7 B6 B5 B4 A7 A6 A5 A4 B3 B2 B1 B0 A3 A2 A1 A0

SUB

S4 S3 S2 S1

A1 A2 A3 A4 B1 B2 B3 B4 CI N CO UT

S4 S3 S2 S1

A1 A2 A3 A4 B1 B2 B3 B4 CI N CO UT INVERT

A₇ A₆ A₅ A₄ A₃ A₂ A₁ A₀

S8 S7 S6 S5 S4 S3 S2 S1 S0

SUB

S4 S3 S2 S1

Y₇ Y₆ Y₅ Y₄ Y₃ Y₂ Y₁ Y₀

0

A

₇

-A

₀

0110 1110

Y

₇

-Y

₀

0110 1110

INV LOGIC

Controlled inverter

(23)

S8 S7 S6 S5 S4 S3 S2 S1 S0

SUB

S4 S3 S2 S1

A1 A2 A3 A4 B1 B2 B3 B4 CI N CO UT ADD/SUB

A₇ A₆ A₅ A₄ A₃ A₂ A₁ A₀

S₇ S₆ S₅ S₄ S₃ S₂ S₁ S₀

S8 S7 S6 S5 S4 S3 S2 S1 S0

SUB

S4 S3 S2 S1

S8 S7 S6 S5 S4 S3 S2 S1 S0

SUB

S4 S3 S2 S1

S8 S7 S6 S5 S4 S3 S2 S1 S0

SUB

S4 S3 S2 S1

S8 S7 S6 S5 S4 S3 S2 S1 S0

SUB

S4 S3 S2 S1

S8 S7 S6 S5 S4 S3 S2 S1 S0

SUB

S4 S3 S2 S1

S8 S7 S6 S5 S4 S3 S2 S1 S0

SUB

S4 S3 S2 S1

S8 S7 S6 S5 S4 S3 S2 S1 S0

SUB

S4 S3 S2 S1

B₇ B₆ B₅ B₄ B₃ B₂ B₁ B₀

ADDITION

A₇A₆A₅A₄A₃A₂A₁A₀

+B₇B₆B₅B₄B₃B₂B₁B₀

SUBTRACTION

A₇A₆A₅A₄A₃A₂A₁A₀

+B

- - - -

₇B₆B₅B₄B₃B₂B₁B₀+1

Binary adder-subtractor diagram

(24)

S8 S7 S6 S5 S4 S3 S2 S1 S0

SUB

S4 S3 S2 S1

A1

A2

A3

A4

B1

B2

B3

B4

CI

N

CO

UT

S4 S3 S2 S1

A1

A2

A3

A4

B1

B2

B3

B4

CI

N

CO

UT

Binary adder-subtractor circuit.

7483