RS-232 TRANSMITTER AND RECEIVER
USING FPGA WITH VHDL CODE
Internal Guide by:-
Prof. Hardik .H .Patel Assistance professor, Department of EC, SRPEC, Unjha. External Guide by:- Mr. Elesh Patel By:- Ankita Patel(090780111007) Kinjal Prajapati(100783111004) Vidhi Patel(090780111001) 8th Semester, B.E (EC), SRPEC, Dabhi – Unjha
CONTENTS
AIM MOTIVATION OVERVIEW OF PROJECT COMPONENT SPECIFICATION STATE DIAGRAM SIMULATION /RESULTS WORK PLAN CONCLUSION FUTURE WORK REFERENCES 8/14/2013AIM
Aim of this project is to transfer data from PC to FPGA
and FPGA to PC using serial communication. For this Serial communication we are using RS-232 for interfacing of PC and FPGA and Using Code of data transfer with VHDL language we Transfer data between FPGA and PC.
Hyper terminal is used for transferring data and for
giving input for receiver section and showing output on hyper terminal for transmitting section.
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MOTIVATION
Many more Data acquisition system are available in the
market Based on DSP ,microcontroller and FPGA etc…But the Faster response, low Power Consumption, less time consuming of FPGA we are going though FPGA.
• Reason for Choosing FPGA based System:
Faster Response.
Low Power Consumption.
Less Time Consuming.
Data Security.
Accuracy.
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OVERVIEW OF PROJECT
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8/14/2013 6 ALTERA MODEL[1]
BLOCK DIAGRAM OF RECEIVER
RX RST CLK 8 BIT DATA R (7 DOWN T0 0)RECEIVR
DATA
BLOCK
8/14/2013 7RECIVER
DATA
BLOCK
RS-232 TX/RX USING FPGA WITH VHDL CODE
BLOCK DIAGRAM OF TRANSMITTER
8 BIT RST CLK TX DATA_TX (7 DOWN T0 0) TRANSMITTER DATA BLOCK8/14/2013 RS-232 TX/RX USING FPGA WITH VHDL CODE 8
HYPER TERMINAL
This is a built in interface in windows which sends and
receives data through the serial port.it has the option of sending through port COM1 and COM2 and also has flexible baud rate.
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COMPONENTS
Altera kit(FPGA)
RS-232
Power Supply
Cyclone QUARTUS II software
PC
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S
PECIFICATION OF ALTERA KIT
5volt external supply.
9600 baud rate.
27 MHZ/25 MHZ frequency.
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DECIDING THE CLOCK AND BAUDRATE
In FPGA clock in not standard. That is ,in FPGA clock is
use by 10MHZ,27MHZ,50MHZ etc..
Baud rate that we are using is 9600.
Also there is miss match between clock and baudrate
so calculate clock by:
Frequency/baud rate= new clock genereted
that is used
in FPGA
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DECIDING THE CLOCK AND BAUDRATE
Here,
27MHZ/9600=2812 cycle
so,there is a 1406 clock cycle for upper cycle and
similarly 1406 clock cycle for lower cycle.
In this way clock and baud rate is decided
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STATE DIAGRAM
S5 IDEAL S0 S1 S2 S3
STATE DIGRAM OF RECEIVER
S7 S6 S4 S8 1 0 1 0 1 Data_r(0)<=rx Data_r(1)<=rx Data_r(2)<=rx Data_r(3)<=rx Data_r(4)<=rx Data_r(5)<=rx Data_r(6)<=rx Data_r(7)<=rx 8/14/2013 16 RST
RS-232 TX/RX USING FPGA WITH VHDL CODE
S5 RST IDEAL S0 S1 S2 S3
STATE DIGRAM OF TRANSMITTER
S7 S6 S4 S8 1 0 1 TX<=data_tx(0) TX<=data_tx(1) TX<=data_tx(1) TX<=data_tx(2) TX<=data_tx(3) TX<=data_tx(4) TX<=data_tx(5) TX<=data_tx(6)
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SIMULATION/RESULT
Design flow
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RS-232 TX/RX USING FPGA WITH VHDL CODE 19
Fig:7 design flow of simulation process[2]
DESCRIPTION OF THE DESIGN FLOW
Design Entry. Synthesis. Functional Simulation. Fitting. Timing Analysis. Timing Simulation. Programming and Configuration.
TESTING WITH HARDWARE
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WORK PLAN
Sr. No Sr. No
Jul-12 Aug-12 Sep-12 Oct-12 W-1 W-2 W-3 W-4 W-1 W-2 W-3 W-4 W-1 W-2 W-3 W-4 W-1 W-2 W-3 W-4 (1) . Selection of project Topic (2) . Introduction (3) .
Detail study in project
work (4) . To study the VHDL Language (5) . To study project by software (6) . Programme practice
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WORK PLAN
8/14/2013 RS-232 TX/RX USING FPGA WITH VHDL CODE 27
Sr.
No Sr. No
Jan-13 Feb-13 Mar-13 Apr-13 W-1 W-2 W-3 W-4 W-1 W-2 W-3 W-4 W-1 W-2 W-3 W-4 W-1 W-2 W-3 W-4 (1)
. Coding of receiver part
(2) .
Implement receiver
code on altera kit
(3) . Coding of transmiter part (4) . Implement transmiter
part on altera kit
(5) .
Implement both code on Xillinx spartan3
code
(6) .
Prepare a report and
CONCLUSION
The FPGA based Transmitter/Receiver data using
serial communication are most of the high fidelity (hi-fi) are maintain using VHDL code design was successfully design by behavioral model.
Here, we get particular output according input what we
are given as and that output is unique for every input.
So that we control many circuits by every unique output
or we operate that many circuits by giving input.
FUTURE WORK
We can also use this method, For transferring file and
documents from one pc to another pc like one pc is data transmit to the FPGA and from FPGA to another pc.
In the transmitter section, There is not stable output
,that means here we get continuous output on the
hyper terminal. so we are trying to get the stable output or static output for transmitter section.
In this session project was based on different code for
TX/RX. So, code will be merged for TX and RX with help of logic loop.
REFERENCES
[1] Cyclone II FPGA Starter Development Board Reference Manual
[2]Stephen Brown and Jonathan Rose(for fpga)s
Department of Electrical and Computer Engineering University of Toronto email: brown |
jayar@eecg.toronto.edu
