Built-In Self-Test (BIST)

The idea of BIST is to build some parts of the test circuitry (i.e. test generators and response analyzers) on the same die as the desired circuit [Sunt96]. Such structures can provide many advantages for testing analog and mixed-signal circuits [Robe97]:

(1) facilitation of design for test,

(2) a hierarchical test solution for all test levels (wafer, package, board and system), (3) a reduction in interconnection length and device loading effects, and

(4) standardization which simplifies the automation and the integration of test into present day CAD facilities.

BIST methodologies are often aimed at specific analog and mixed signal circuits such as ADC/DAC converters and filters. In this section, we will discuss the relevant BIST schemes reported in the test literature.

• BIST for mixed-signal circuits

The hybrid Built-In Self-Test (HBIST) [Ohle91, Ohle96] is used to test mixed-signal circuits which include a complex digital kernel system and peripheral analog sub-circuits at the input and the output (A-D-A structure). Multiplexers implemented by CMOS transmission gates are used to isolate the circuit under test from the environment and place it in the test mode. The test process is performed in two sequential steps, the first step for testing the digital kernel sys- tem and the second for testing the analog sub-circuit. In this structure, shift registers such as

“BILBO” or “LFSR” registers and the multiple input signature register (MISR) are used to achieve the test pattern generation and the signature analysis on the chip.

The mixed Analog Digital Built-In Self-Test (MADBIST) [Tone93, Robe97] is based on the A- D-A structure and employed for mixed-signal telecommunication ICs such as MODEM and CODEC for the signal-to noise ratio (SNR) test. The digital kernel system of this structure is a DSP. The test stimuli is generated relying on the oversampling sigma-delta modulators [Veil95, Robe95, Huar98, Dufo99, Dufo00]. The single tone signal such as sine wave or multi- tone test signals [Lu94] can be generated using the sigma-delta modulator. The evaluation of on-chip measurements such as the SNR can be carried out using a kernel DSP.

The Histrogram-based Analog Built-In Self-Test (HABIST) [Fris97] assumes the CUT is embedded between D/A and A/D. The histrogram of the CUT is used as a signature. The test stimulus vector can be generated from an external generator or a built-in generator. An access method to each test point is provided, and the histrogram of the signal at each test point is gen- erated. Finally, the signature of the CUT is obtained by comparing the histrogram of the CUT with the one expected.

The oscillation Built-In Self-Test (OBIST) [Arab97] is based on an oscillation-test strategy which converts the circuit under test into an oscillator in the test mode. The oscillation fre- quency of the circuit under test is evaluated on-chip by a digital circuitry and compared with a fault-free one to decide whether the CUT is faulty or not. The main advantage of this structure is that it does not require test vector generators.

• BIST for analog circuits

BIST techniques for analog circuits are proposed for specific classes of circuits. A BIST approach for switched-capacitor filters is proposed in [Huer93b]. This approach exploits the fault tolerance technique (hardware redundancy) using partial replication of the circuit under test. The resulting continuous signals can be compared in the time domain via a circuit voter. Also the authors in [Chat93] utilize the hardware redundancy to develop a BIST (concurrent error detection) scheme based on the continuous checksum for linear analog circuits repre- sented by state variable equations.

In [Chao95], the authors suggest BIST and fault diagnosis techniques for analog circuits in the frequency domain. This scheme exploits the following circuits: (1) the white noise generator as a test generator, (2) the programmable window filter to select the frequency range of inter- est, and (3) the peak detector to detect the peak response at a certain frequency point or in a frequency range.

In [Mir97], a BIST methodology was developed for sigma-delta modulators based on a circuit reconfiguration and comparison. In this methodology, a test stimuli generator is assumed to be available on-chip to generate single or multi-tone test signals. This structure is used for the production test due to the short time testing as well as not needing any digital signal process- ing capabilities. In [Mir96b], unified BIST approach is suggested for fully differential analog circuits based on boundary scan techniques. In [Chat96], a low cost DC BIST technique is developed for linear circuits. A simple DC generator and error checking circuitry are imple- mented on-chip.

In [Vari00], the authors propose a BIST structure to improve the fault detectability in the time domain. Pulse trains with a varying pulse width are generated using a digital LFSR serving as transient test stimuli for the CUT. The signature is a sequence of digital bits resulting from the comparator with a reference voltage. Traditional scan techniques can be used to analyze the obtained signature.

The main shortcoming of the BIST technique is the need for extra on-chip hardware which may cause the degradation of the system performance and leads to an increase of the chip area overhead.