Design for Testability (DfT)

Test nodes play a great role for testing analog and mixed-signal circuits. Test nodes may be required for several purposes:

1) to excite the test signals (stimuli) at controllable nodes into embedded modules, 2) to perform measurements at observable nodes to obtain the circuit responses, and 3) to isolate the faults in fault diagnosis approaches.

Due to accessibility limitations resulting from increasing the integrity of the ICs, DfT method- ologies are required to improve the circuit testability in terms of improving controllability and observability of internal nodes. As a result, DfT techniques are aimed at accessing the internal nodes for testing purposes by adding an additional hardware in order to support high fault detectability and reduce the total test costs of ICs by reducing testing time.

DfT techniques can be divided into two categories: reconfiguration-based DfT and accessibil- ity-based DfT [Chat97].

3.5.5.1. Reconfiguration-Based DfT

Reconfiguration-based DfT techniques rely on a reconfiguration of the circuit under test to improve their testability. These techniques were developed to improve the controllability and observability of internal nodes for specific classes of circuits such as active filter with cas- caded stages [Soma90], switched-capacitor filters [Soma94, Huer93b], operation amplifier [Brat95, Reno98].

3.5.5.2. Accessibility-Based DfT

Accessibility-based DfT techniques are used to improve controllability and observability for analog and mixed-signal circuits by extending the digital DfT techniques such as scan chain, boundary scan, and test bus to test analog and mixed-signal circuits.

• Scan Chain Technique

In scan chain techniques (see Figure 3-8) [Kerk94], there are two modes, one for tests and the other for normal operations. The nodes of interest are connected to an analog shift register through switches and buffers. The switches are used to isolate the analog shift register from the circuit during normal operation. The buffers are used to minimize the influence of the test hardware on the measured nodes.

In the first step of the test mode, the test data are sampled at measured nodes and stored in capacitors by closing the switches to the circuit under test and opening the switches of the ana- log shift register. In the second step of the test mode, the connecting switches are open and switches of analog shift register are closed. In this way the stored information in the capacitors can be shifted by a simple digital shift register to a scanning output. This technique is referred to as Bucket-Brigade-Like Devices.

An improvement to this technique can be carried out using the Charge-Coupled Device (CCD) to implement the analog shift register. The principle of this technique is similar to the Bucket- Brigade-Like Devices technique except that the discrete analog information is handled in the form of charges. The conversion of input voltages and currents into charges is carried out by charge converters (CC). At the output the charges are converted back into voltages and cur- rents.

• Boundary Scan

Boundary scan techniques utilize ADC and DAC converters which are existed in many mixed- signal circuits. ADC and DAC converters are used to digitize the analog outputs before storing them in the scan cell registers and shifting them to external pins, and to convert digitized ana- log inputs to be shifted into the scan path to primary output as shown in Figure 3-9 [Milo98].

Figure 3-8: Scanning Techniques [Kerk94] Circuit Under Test

S

S S S

node 1 node 2 node n

Analog Shift Register

Primary Input Primary output

Scanning Input Scanning Output

The analog inputs can be controlled by primary inputs, and the analog outputs can be observed by primary outputs of the analog part.

In this technique, the analog tests are separated from digital ones, furthermore, the analog parts of a complex mixed-signal circuit should be divided into analog blocks i.e. filters, opera- tion amplifiers, ADCs, DACs, phase-locked loops and others to enhance their ability of identi- fying the faulty blocks. The identification of the faulty blocks can be achieved using analog shift registers and storage elements similar to the scan chain techniques.

• Analog Test Bus

The analog test bus is widely used to access the internal nodes of a mixed-signal circuit where the nodes of interest are provided for controlling the input stimuli (analog test bus AT1) and observing the associated response (analog test bus AT2) as shown in Figure 3-10 [Robe97].

Figure 3-9: Boundary Scan Techniques [Milo98]

Figure 3-10: An analog test bus configuration [Robe97] Digital

Analog Analog

ADC DAC

Analog PO Analog PI

Scan In Scan Out Boundary Scan Path

Digital IOs Boundary Scan Cells AT₁AT_{2 Dout Din} Analog Core Out In Transmission gate F/F F/F

Recently, a standard analog test bus for mixed-signal circuits called IEEE P1149.4 was defined. The IEEE P1149.4 is extending to IEEE 1149.1 for digital circuits [Soma96c, Sunt96, Sunt99, Osse99, Kac03]. The IEEE 1149.4 standard analog test bus can detect open and short faults in a board’s wiring interconnection which consist of 80%-90% of all board failures. The standard is aimed at board level, thus the other analog test problems at other IC test levels (cf. Section 3.2) are not solved using this standard.

In summary, the IC developers are often not very willing to insert DfT structures into their analog circuitry because of the risk of degrading the performance, especially for high fre- quency and high performance circuitry. Moreover, the DfT approaches require additional cir- cuitry which increase the chip area. The additional circuitry increases the die manufacturing costs and the probability of faults in the chip.