sides of traffic lights is given below the dotted line in Fig. 1. Here, the 4-bit and 2-bit counters are joined together to form a 6-bit counter. Outputs of the 2-bit counter, representing two MSB digits, are connected to a decoder that has two con-trol inputs and four outputs. The decoder activates one of the four outputs depend-ing upon the input (00 or 01 or 10 or 11) of 2-bit counter.
Each output of the decoder can drive clock-2 at a different frequency. These four outputs are connected to the four sides of traffic lights and select each side one af-ter another. The time in which the pre-ceding 4-bit counter counts from 0000 to 1111 (16 counts) is the time allowed for each side of traffic lights.
First, when the 4-bit counter counts from 0000 to 0001 (two counts), yellow light of the selected side will turn ‘on’.
From count 0010 to 1101 (12 counts), green light will turn ‘on’. Again from 1110 to 1111 count (two counts), yellow light will turn ‘on’. Meanwhile, in the other three sides of traffic lights that are not selected by the decoder, red light will be
‘on’. Similar operation will repeat for each
TABLE I
Functional Summary of Part I Circuit
Time Output Output at Output at Activated RA Street Traffic of IC1(a) QA of IC5 QH of IC5 Resistance Light Light
(LED1) Mode
Evening HIGH LOW LOW RA1 OFF A
After 8 cycles of clock-1 HIGH HIGH LOW RA1 ON A
(Delay time for streetlight)
After 120 cycles of clock-1 HIGH HIGH HIGH RA1 ON B
(Delay time for night)
Morning LOW HIGH HIGH RA2 ON B
After 8 cycles of clock-1 LOW LOW HIGH RA2 OFF B
(Delay time for streetlight)
After 120 cycles of clock-1 LOW LOW LOW RA2 OFF A
(Delay time for day)
Evening HIGH LOW LOW RA1 OFF A
Delay times and evening/morning times are adjustable.
A: Continuous traffic light mode B: Blinking yellow light mode
Fig. 3: Actual-size, single-sided PCB for the circuit in Fig. 2
Fig. 4: Component layout for the PCB
Thus the 6-bit counter will clear when QH output is high or the reset button is pressed. The reset key, when pressed, also causes counter IC4 and shift register IC5 of Part I to be cleared. QH output of IC5 is connected to reset pin 4 of clock-3 (IC12). The output of this clock is con-nected to inverter gate N4. Low QH (dur-ing day) activates the 6-bit counter and deactivates clock-3. Due to this, the out-put of inverter gate N4 will be high dur-ing the day. This output is connected to one of the inputs of four AND gates H1 through H4. Each of these AND gates is a part of one side of traffic light circuit.
NAND gates B1, B2, and B3 are con-nected to the outputs of flip-flops F2, F3, and F4 of the 6-bit counter. The final out-put of this circuit (the outout-put of gate B2) will be high whenever the first four bits of the counter are 1110 or 1111 or 0000 or 0001 (14 or 15 or 0 or 1), otherwise it will be low. Accordingly, inverter N5 out-put will be low for the above contents of the counter and high for the remaining contents (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, or 13).
The output of NAND gate B2 and its complement (the output of inverter N5) are connected to NOR gates X2 (=E2, J2, K2, and M2) and X3 (=E3, J3, K3, and M3) of the each side of traffic light, re-spectively. Other inputs of X2 and X3 NOR gates are common.
The last two flip-flops (F5 and F6) of the 6-bit counter are connected to four NAND gates G1 through G4 in such a way that the output of G1, G2, G3, and G4 will be low when last two counter bits are 00 (0), 01 (1), 10 (2) and 11 (3), re-spectively. For example, when last two bits of counter contents are 01 (1), only output of NAND gate G2 will be low and others (G1, G3 and G4) will be high.
The complements of these four NAND gate outputs (obtained from collectors of transistors T3 through T6) are connected to the four RA resistors of 555 clock-2.
Other terminals of these four resistors are connected to the anodes of diodes D8, D10, D12, and D14, while their cathode terminals are all connected to pin 7 of 555 clock-2 (IC6). This is analogous to the fashion in which RA1 and RA2 have been connected in Part I in the clock-1 circuit.
When last 2-bit counter contents are 00, RA3 (=R21+R25+VR7) will become ac-tive and other three resistors RA4, RA5, and RA6 will become inactive. Therefore of the selected side in its turn.
Reset pin of clock-3 and clear pins of the 6-bit counter are controlled by output QH from IC5of Part I. At night, QH will go high and the 6-bit counter will clear, while clock-3 becomes active. As a result, yel-low lights of the four sides of traffic light will blink simultaneously.
The detailed circuit diagram is given below the dotted line in Fig. 2. The
ac-tive-‘low’, clear input signal for the 6-bit counter (formed by dual J-K flip-flops inside IC7 through IC9) is provided from the output of NOR gate E1, whose one input is connected to QH output of shift register IC5 of Part I and the other input is connected to the output of in-verter gate N3. The input of inin-verter gate N3 is connected to push-to-on reset switch S1.
Fig. 6: The traffic and street light controller
Fig. 5: Connections for vehicular traffic lights and pedestrians’ signals
the time period of clock-2 of the 6-bit counter will be dependent upon RA3.
Similarly, when last 2-bit counter con-tents are 01 or 10 or 11, the time period of clock-2 will be dependent upon RA4 (=R20+R24+VR6), RA5 (=R19+R13+VR5), and RA6 (=R18+R12+VR4), respectively.
The output of NAND gate G1 is con-nected to the common input of NOR gates E2 and E3 of the first side of traffic light and complements of the outputs of other three NAND gates G2, G3, and G4 are connected to one of the inputs of NOR gates J1, K1, and M1, respectively. The other inputs of these NOR gates are con-nected to QH output of IC5. Red and green lights are connected to the outputs of NOR gates X4 (=E4, J4, K4, and M4) and X2 (=E2, J2, K2, and M2), and yellow light is connected to AND gate of each side of the traffic light.
During daytime, the outputs of AND gates (which are connected to yellow lights) will be the same as the outputs of NOR gates X3(=E3, J3, K3 and M3) of each side, because one of the inputs of AND gates is high in daytime. Low QH (during daytime) forces NOR gates J1, K1, and M1 to work as the inverter gate for the other inputs. Therefore the com-mon input of NOR gates X2 and X3 of
sides 1, 2, 3, and 4 will be the same as the output of NAND gates G1, G2, G3, and G4, respectively.
Let us suppose that initially the con-tents of the 6-bit counter are 000000.
When the counter counts up from 000000 to 001111, the output of NAND gate G1 will be low and that of other NAND gates G2, G3, and G4 high. Due to this, RA3 will be active and the time period of clock-2 of the counter will be according to RA3.
The high output of NAND gates G2, G3, and G4 forces the output from NOR gates J2, K2, M2 and J3, K3, M3 to low state. These low outputs are input to NOR gates J4, K4, and M4, due to which the output of these gates will be high. It means yellow and green lights will be ‘off’
and red light will be ‘on’ in the remaining three sides of the traffic light.
Due to the low output of NAND gate G1 (which is connected to the common input of NOR gates E2 and E3 of first side), the output of NOR gates E2 and E3 of first side will depend on the output of the three-NAND gate circuit (comprising gates B1, B2, and B3).
When the 6-bit counter counts from 000000 to 000001, the output of the three-NAND gate circuit will be high, which is
connected to NOR gate X2 of each side and its complement is connected to NOR gate X3 of all sides. Due to this, the out-put of NOR gate E3 will be high and those of NOR gates E2 and E4 low. In short, during the count period 000000 to 000001 yellow light of the first side of traffic light and red light of the other three sides will be ‘on’.
When the counter counts up further from 000010 to 001101, the output of the three-NAND gate circuit will be low and its complement will be high. Due to this reason, the output of NOR gate E2 will go high and that of NOR gates E3 and E4 low. Therefore, when counter contents in-crement from 000010 to 001101, green light of first side and red light of all the other sides will be ‘on’.
Again from 001110 to 001111, the out-put of three-NAND gate circuit will go high, due to which yellow light of first side and red light of the other sides will turn ‘on’. The time in which the counter counts from 000000 to 001111 can be ad-justed by RA3. The functioning of the other three sides of the traffic light is similar.
Daytime functional summary of the circuit for signal generation for four sides of traffic light is given in Table II. Change in RB resistance (VR3+R11) of clock-2, being common for all sides, will change the time allowed for each side of traffic light by an equal amount.
At night, QH output of IC5 will be high, due to which the 6-bit counter will clear and clock-3 will start working. The out-put of NOR gates J1, K1, and M1 and NAND gate G1, and the complement of the output of the three-NAND gate cir-cuit will be low. This forces the output of NOR gate X3 of each side to high state.
This high output will turn off all the red lights and give high signal to one of the inputs of AND gates H1 through H4. The other input of these AND gates is con-nected to the complement of clock-3, due to which all the four sides of yellow light will blink.
The four sides of traffic light signals can be used for driving vehicular traffic signals for straight, right, and left turns and pedestrian’s signals. Fig. 5 shows one of such possible connections of vehicu-lar and pedestrian’s signals. The complete circuit in model form is shown in Fig. 6.
Actual-size, single side PCB for the circuit shown in Fig. 2 is given in Fig. 3 with its component layout in Fig. 4.
TABLE II
Daytime Functions of Part II Circuit Counter Decoder output Activated RA Glowing LEDs contents G1 G2 G3 G4 resistance
000000 - 0 1 1 1 RA3 4,6,9,12 (Yellow light of 1st side and
000001 red light of other sides)
000010 - 0 1 1 1 RA3 2,6,9,12 (Green light of 1st side and
001101 red light of other sides)
001110 - 0 1 1 1 RA3 4,6,9,12 (Yellow light of 1st side and
001111 red light of other sides)
010000 - 1 0 1 1 RA4 3,7,9,12 (Yellow light of 2nd side and
010001 red light of other sides)
010010 - 1 0 1 1 RA4 3,5,9,12 (Green light of 2nd side and
011101 red light of other sides)
011110 - 1 0 1 1 RA4 3,7,9,12 (Yellow light of 2nd side and
011111 red light of other sides)
100000 - 1 1 0 1 RA5 3,6,10,12 (Yellow light of 3rd side and
100001 red light of other sides)
100010 - 1 1 0 1 RA5 3,6,8,12 (Green light of 3rd side and
101101 red light of other sides)
101110 - 1 1 0 1 RA5 3,6,10,12 (Yellow light of 3rd side and
101111 red light of other sides)
110000 - 1 1 1 0 RA6 3,6,9,13 (Yellow light of 4th side and
110001 red light of other sides)
110010 - 1 1 1 0 RA6 3,6,9,11 (Green light of 4th side and
111101 red light of other sides)
111110 - 1 1 1 0 RA6 3,6,9,13 (Yellow light of 4th side and
111111 red light of other sides)
Note. The two MSB digits determine the side, while the next four digits determine the time for which the mentioned LEDs are ‘on’.
Calibration
Set preset VR8 in such a position that the output of comparator IC1(a) switches from one state to the other at a particular in-tensity of natural light. Variable resistors VR1 and VR2 can be calibrated on a time scale using the following relationships:
VR1 = (1/120) (1.44 TNight/220) 106 – (122.2) 103
VR2 = (1/120) (1.44 TDay/220) 106 – (122.2) 103
where TDay and TNight are delay times in seconds (time interval between switching of comparator IC1(a) and when the traf-fic light switches its mode) corresponding to day and night, respectively.
Variable resistors VR4 through VR7 can be calibrated on a time scale by the following relationship:
VR (4,5,6,7) = (1/16)(1.44 T/6.8) 106 – (122.2) 103 – 2 VR3
where T is the time allowed (in seconds) for the side of traffic light in which the corresponding variable resistance is con-nected.
Possible enhancements. Stepper motor-driven wiper can be used for
clean-ing the dust over the light sensor durclean-ing night time. Control signal for this can be obtained from the shift register.
Also, time-controlling variable resis-tors VR4 through VR7 of Part II can be replaced by LDRs with a small light source whose light intensity varies accord-ing to the strength of traffic on each side.
Implementation of this system requires traffic-sensing sensors. This system will
change the time of each side of traffic light according to the strength of traffic.
Further, the present circuit being only a demonstration model uses LEDs for lights. To drive high-wattage lights, one can easily boost the signals used for driv-ing the LEDs to operate solidstate or electomechanical relays. ❏ The author is an M.Tech. from IIT, Delhi, and is currently pursuing his Ph.D studies.
October
2001
Circuit Ideas
2001
S.C. DWIVEDI
T
he circuit presented here can be used to control the speed of fans using induction motor. The speed control is nonlinear, i.e. in steps. The current step number is displayed on a 7-segment display. Speed can be varied over a wide range because the circuit can alter the voltage applied to the fan motor from 130V to 230V RMS in a maximum of seven steps.The triac used in the final stage is fired at different angles to get different voltage outputs by
applying short-dura-tion current pulses at its gate. For this pur-pose a UJT relax-ation oscillator is used that outputs sawtooth waveform.
This waveform is coupled to the gate of the triac through an o p t o c o u p l e r (MOC3011) that has a triac driver output stage.
Pedestal voltage control is used for varying the firing angle of the triac.
The power supply for the relaxation oscilla-tor is derived from the rectified mains via 10-kilo-ohm, 10W series dropping/limit-ing resistor R2.
The pedestal voltage is derived from the non-filtered DC through optocoupler 4N33.
The conductivity of the Darlington pair transistors inside this optocoupler is varied for getting the pedestal voltage. For this, the positive sup-ply to the LED inside the optocoupler is
ured as an astable multivibrator to pro-duce rectangular clock pulses for IC5, while NAND gates N1 and N2 generate the active-low count enable (CE) input us-ing either of push-to-on switches S1 or S2 for count up or count down operation, re-spectively, of the BCD counter.
Optocoupler 4N33 electrically isolates the high-voltage section and the digital section and thus prevents the user from shock hazard when using switches S1 and S2. BCD-to-7-segment decoder CD4543 is used for driving both common-cathode and common-anode 7-segment displays. If phase input pin 6 is ‘high’ the decoder works as a common-anode decoder, and if phase input pin 6 is ‘low’ it acts as a common-cathode decoder.
connected via different values of resistors using a multiplexer (CD4051).
The value of resistance selected by the multiplexer depends upon the control in-put from BCD up-/down-counter CD4510 (IC5), which, in turn, controls forward bi-asing of the transistor inside optocoupler 4N33. The same BCD outputs from IC5 are also connected to the BCD-to-7-seg-ment decoder to display the step number on a 7-segment display.
NAND gates N3 and N4 are