The capacitance measurement mode.
During the capacitance measurement mode, switches S1 through S5 are kept slided towards position ‘C’. The unknown capacitor is placed across CUT terminals.
Ganged switches SR1 and SR2 are used for capacitance measurement. Position 1 is used for capacitance range of 1 pF to 9999 pF (≈10 nF), position 2 for capaci-tance range of 1 nF to 9999 nF (≈10 µF), and position 3 for capacitance range of 1 µF to 9999 µF.
Switch SR1 selects 1 mega-ohm charg-ing resistor in its positions 1 and 2, while switch SR2 selects a frequency of 1 MHz in position 1 and a frequency of 1 kHz in position 2 for the counter operation. In
position 3, 1-kilo-ohm charging resistor R6 is selected by SR1, while SR2 selects 1 kHz as the frequency for counter opera-tion.
Ganged rotary switches SR3 and SR4 are used for frequency measurement mode only. (EFY note. As decimal indication is not required during capacitance mea-surement, one might have an additional
PARTS LIST Semiconductors:
IC1 - NE555 timer
IC2, IC3 - CA3140 high-input impedance op-amp IC4 (A-D) - 7408 AND gate
IC5 - MM74C925 4-digit counter/
7-segment driver IC6 - 74LS121 monostable MV IC7-IC9 - 74LS90 decade counter
(divide-by-10) IC10 - 7476 JK flip-flop IC11 - 7805 regulator +5V D1-D5 - 1N4007 rectifier diode D6 - 1N4148 switching diode
LED1 - Red LED
T1-T5 - BC547B npn transistor
T6 - BS107 FET
Resistors (all ¼ watt, ±5% carbon, unless stated otherwise)
R1 - 2.2-kilo-ohm R2, R5 - 1-mega-ohm R3, R8, R24 - 4.7-kilo-ohm R4, R20 - 10-kilo-ohm R6, R7, R18
R21 - 1-kilo-ohm
R9-R16 - 220-ohm R17 - 20-kilo-ohm R19 - 100-kilo-ohm R22, R23 - 560-kilo-ohm VR1 - 1-kilo-ohm preset Capacitors:
C1 - 15µF, 25V electrolytic C2 - 0.01µF ceramic disk C3 - 10nF ceramic disk C4 - 10µF, 250V electrolytic C5 - 1000 µF, 25V electrolytic C6 - 100µF, 25V electrolytic C7, C8 - 22 pF ceramic C9 - 0.01µF ceramic Miscellaneous:
X1 - 230 AC primary to 9-0-9 volt, 500mA secondary trans-former
XTL - 1MHz quartz crystal S1-S5 - Slide switch S6, S7 - Push-to-on switch
SR1-SR2 - Ganged 3-way, 2-pole rotary switch
SR3-SR4 - Ganged 3-way, 2-pole rotary switch
DIS1-DIS4 - LT543 common-cathode, 7-segment display
Fig. 1: Circuit diagram for digital capacitance-cum-frequency meter
‘off’ position for SR3/SR4 ganged rotary switch.)
IC1 is a monostable multivibrator based on timer NE555 and is meant for capacitance measurement only. In normal condition, the low output of the monostable turns on the FET (BS107) switch. So the capacitor under test gets
shorted via the FET switch. As and when triggered by the momentary push-to-on operation of start switch S6, the monostable provides a pulse of 15-second duration. As soon as its output goes high, it switches off FET switch. Simulta-neously, it takes pin 5 of AND gate IC4A high.
Now let us examine the conditions at IC2 and IC3 (both CA3140 op-amps). The voltage across CUT, after being buffered by IC2, is fed to the inverting input of IC3 wired as a comparator. The non-in-verting input of IC3 is biased at 0.63Vcc, which is set accurately by 1-kilo-ohm pre-set VR1. Now the capacitor begins to charge. As soon as the voltage across the capacitor crosses 0.63Vcc (i.e. 3.15 volts with Vcc = 5 volts), the output of IC3 goes low. Thus the output of IC3 and also that of AND gate IC4A remains high un-til the capacitor charges to 63 per cent of Vcc in one RC time.
Latch-enable (LE) pin 5 of counter IC5 (74C925) connected to pin 6 of IC4A re-mains high to pass the clock selected via rotary switch SR2 and coupled to CL (clock) pin 11 of IC5 via AND gate IC4B.
It goes low after one CR time to latch its count as the output of IC3 goes low. Thus the number of cycles from the frequency source passed over one CR time is re-corded in the counter and gets displayed.
For precise generation of 1MHz fre-quency, a 1MHz crystal oscillator is wired around Schmitt inverter gates N3 and N4.
The oscillator output is routed via AND gate IC4C to slide switch S2 and rotary switch SR2 position 1. In capacitance (C) position of switch S2, this signal, after division by three decade counters IC7, IC8, and IC9 (7490), which are common to both frequency and capacitance meter modes, provides 1kHz signal at pin 12 of IC9, which, in turn, is extended to posi-tions 2 and 3 of switch SR2. (Note. The outputs of IC10 are not used during ca-pacitance measurement. IC10 comes into play only during the frequency measure-ment as explained later.)
The NE555 timer used as a monoshot ensures the capacitance measurement in an easy and automatic manner. The LED connected to AND gate IC4D glows dur-ing the chargdur-ing of the capacitor. Durdur-ing the measurement of high-value capaci-tances, it may take several seconds to charge to 0.63Vcc. For low-value capaci-tances, the LED glows for just a moment after pressing start switch S6. If the LED goes off after the start button is pressed, it indicates that the measurement is over.
You can reset NE555 timer using switch S7 if you want to make another measurement. If this switch is not pro-vided/operated, you would have to wait for at least 15 seconds until NE555 timer becomes normal. Alternatively, you will Fig. 3: Actual-size, single-sided PCB layout for digital capacitance-cum-frequency meter
Fig. 2: Internal block diagram and functional description for IC 74C925
Fig. 4: Component layout for the PCB
of 0.1 second, 1 second, or 10 seconds in positions 1, 2, and 3, respectively, of switch SR3. Q output of IC10 is used to enable counter IC5.
The resetting of counter-cum-display IC5 is accomplished by the narrow out-put pulse from IC6 (74121), which is gen-erated by the leading (rising) edge of Q output of IC10 connected to its B input (pin 5) via switch S5. Thus at the begin-ning of each counting period, IC5 is reset.
IC5 (74C925) is TTL-compatible with a multiplexed 4-digit, 7-segment display driver. Its internal block diagram and functions are described in Fig. 2. The maximum frequency display in positions 1, 2, and 3 of ganged switches SR3 and SR4 is limited to 99.99 kHz, 9.999 kHz, and 999.9 Hz. The decimal point position is fixed by switch SR4.
Calibration and testing. Connect a multimeter to the non-inverting terminal of IC3 and set the point at 0.63Vcc = 3.15 volts using 1-kilo-ohm preset VR1. To test the capacitance meter, use a 470pF poly-styrene capacitor with one per cent toler-ance.
Precaution. Try to screen the mains transformer from the input. Place the transformer at a place where the chances of its interference with the input are mini-mal or nil. While measuring the fre-quency, the frequency source under test should not be touched or loaded to avoid affecting its frequency due to stray ca-pacitance associated with the test leads.
An actual-size, single-sided PCB for the circuit of Fig. 1 is shown in Fig. 3, with its component layout shown in
Fig. 4. ❏
against high voltage.
R21 is test selected to get proper 100 Hz rectangular wave form at the output of gate N2. This 100Hz signal is divided by decade counters IC7, IC8, and IC9 to obtain 10Hz, 1Hz, and 0.1Hz frequencies.
The frequency selected via rotary switch SR3 is then divided by 2 by JK flip-flop 7476 (IC10) so as to provide a gate time have to switch off the complete circuit
and then switch it on again.
Frequency counting. In place of 1MHz oscillator, a 100Hz full-wave recti-fied (pulsating DC) after being shaped by Schmitt inverter N2, is used as the mas-ter clock to provide the required time bases. The voltage divider network of re-sistors R20 and R21 protects gate N2
RUPANJANA