Fig. 1 shows the circuit for propor-tional load control using a PC. Triac BT139 used in the AC circuit controls the amount of power transferred to the load.
The amount of power is controlled by vary-ing the phase angle of triac triggervary-ing.
The mains AC waveform is shown in Fig. 2(a). The triggering of the triac is done with respect to the zero crossing of the AC signal. Every time the AC wave-form crosses zero voltage line, the triac has to be triggered by the pulse at the gate. Once this is done, the triac latches and remains ‘on’ until the AC waveform reaches 0V. By delaying the triggering of the triac, the amount of power delivered to the load within an AC cycle (180 degrees) can be altered.
The digital output data at the paral-lel port (controlled by the program) is con-verted into analogue equivalent using latch IC 74HC573 (IC3) and an R-2R ladder network. The analogue voltage varies from 0 to 5V depending on the digital input from the parallel port. A digital value of 255 (maximum value) gets converted into an analogue equivalent of 5V, and 0 (minimum value) gets converted into 0V.
The analogue value is compared against the time base generated by a stable ramp generator and gets converted into corresponding time delay. In case the ramp and the analogue equivalent are the
same, comparator N4 gives a pulse to opto- Fig. 1: The circuit for proportional load control using PC
isolated diac MOC3022 (IC4), which, in turn, triggers the triac. This cycle is re-peated for every zero-crossing in the AC line.
The MOC3022 is an optically-coupled isolator consisting of a GaAs infrared emitting diode (LED) and a light-activated silicon bilateral switch, mounted in a standard 6-pin dual-in-line package, that controls triggering of the triac.
A snubber circuit removes all EMI emissions from the AC line and also pro-tects the triac. It comprises capacitor C3 and resistor R12.
Zero-crossing detection. Opto-isola-tor H11G1 (IC1) is used as the zero-cross-ing detector. It is an optically-coupled isolator consisting of an infrared LED and a high-voltage npn silicon Darlington phototransistor that has an internal base-emitter resistor to optimise switching speed.
The AC signal from mains is rectified by a full-wave bridge rectifier comprising diodes D1 through D4. The rectified out-put is pulsating DC (shown in Fig. 2(b))
having the same amplitude as the AC waveform, except that now it varies from 0 to 220Vrms, 100 times in a second. It is fed to the internal LED of opto-isolator IC1 through current-limiting resistor R1.
The light emitted by the LED triggers the internal transistor of IC1 and it gives out a digital signal. The digital signal is used as a zero-crossing signal (shown in Fig.
2(c)).
Thus, when the AC waveform crosses zero, the inbuilt Darlington transistor pair turns off, setting the output to high (logic 1). And when the AC signal waveform picks up in amplitude either during posi-tive half cycle or negaposi-tive half cycle, the internal LED of IC1 conducts, switching on the internal transistor of IC1 and set-ting the output to low (logic 0). Zener di-ode ZD1 limits the signal to 5.6 volts.
Digital interface. The low-cost 74HC573 D-type octal latch (IC3) is used as the digital input interface for the cir-cuit. Its input is connected to a 25-pin D-type connector that plugs into the computer’s parallel port (LPT1) at the
back of the PC. Pins 2 through 9 form the 8-bit data output port, that can be used to output data through it. Base address of the first parallel port (LPT1) is 0378 in hexadecimal (hex).
At every zero crossing of the signal, new data from the computer is latched on the output of IC3. Comparator N1 gener-ates a latch-enable signal for IC3 at every zero-crossing of the AC signal waveform.
The output of the latch feeds the R-2R ladder network. The ladder network com-prises resistors R19 through R28. The digi-tal-to-analogue converter (DAC) is the com-bination of latch IC3 and the R-2R net-work.
Ramp generator. A capacitor charged at a constant current (I) develops a linear voltage (V=I×t/C) across it. When a 10nF capacitor (C2) is charged at a con-stant current of 5 μA for a period of 10 ms, it develops 5V across it. This is the basis of the ramp generator operation.
Transistor T1 (BC547) is wired to de-liver a constant current irrespective of the load resistance. The rate of constant cur-PARTS LIST
Semiconductors:
IC1 - H11G1 optically coupled isolator
IC2 - LM339 comparator IC3 - 74HC573 octal D-type latch IC4 - MOC3022 optically coupled
bilateral switch T1 - BC547 npn transistor T2 - BEL188 pnp transistor TRIAC - BT139 triac
D1-D10 - 1N4007 rectifier diode ZD1 - 5.6V, 1W zener diode ZD2 - 6.0V, 0.5W zener diode Resistors (all ¼-watt, ±5% carbon, unless stated otherwise):
R1 - 47-kilo-ohm, 2W R2, - 10-kilo-ohm
VR1 - 47-kilo-ohm trimport Capacitors:
C1 - 0.1μF ceramic disk C2 - 10nF ceramic disk C3 - 0.01μF ceramic disk C4 - 220μF, 25V electrolytic Miscellaneous:
X1 - 230V AC primary to 9V-0-9V, 200mA secondary transformer
F1 - 100mA fuse
- 25-pin D-type connector
Fig. 2: Waveforms at different stages in the circuit
rent is set by resistor R7 and trimpot VR1.
By synchronising the start of charging of the capacitor and the zero crossing of AC signal, a linear ramp in sync with the AC signal (refer Fig. 2(d)) is generated. (In the waveform shown in Fig.
2(d) the DAC output is superimposed over the ramp.) At the end of the cycle, com-parator N2 triggers pnp transistor T2 (BEL188), which discharges capacitor C2 to prepare it for another cycle. During this brief period, N3 switches off constant-current generating transistor T1 (BC547).
The ramp voltage is fed to one of the inputs of comparator N4 and the other input of the comparator is connected to the output of the DAC (R-2R ladder).
When the ramp voltage reaches the R-2R ladder voltage (analogue equivalent of the digital input from the computer’s LPT1 port), comparator N4 goes low and the internal LED of IC4 conducts to trigger triac BT139 with the help of opto-isolated diac MOC3022 (IC4).
Figs 2(e) and (f) show the outputs of comparator N4 and the triac, respectively.
In Fig. 2(f), the shaded portion of the wave-form represents the output during the con-duction state of the triac.
Power supply. The AC mains supply is stepped down by transformer X1 to de-liver a secondary output of 9V-0-9V AC at 200 mA. The output of the transformer is rectified by a full-wave rectifier. Capaci-tor C4 acts as a filter to eliminate ripples.
Zener ZD2 provides regulated 6V power supply for the circuit excluding compara-tor. A 12V DC supply is applied to the comparator.
Example
Let the digital input be 1000 0000 (128 in hex), which is half the maximum 8-bit value of 1111 1111 (255 in hex).
The analogue equivalent of the R-2R ladder network is 2.5V, for a 5V supply.
At zero crossing (t=0), the voltage across capacitor C2 is 0V with respect to 5V. (The ramp voltage has a negative slope, and, as time progresses, the volt-age across the capacitor decreases with respect to ground.)
The 5μA charging current (I) is set by resistor R7 and trimpot VR1 that are con-nected in series with the emitter of tran-sistor T1 (BC547). Thus the time taken by the ramp voltage to reach 2.5V is:
t = C×V/I
= 5 ms
This is half the 10ms time duration of one rectified AC cycle.
After 5 ms, comparator N4 triggers triac BT139 and only half the power is delivered to the load. Thus the triac is triggered proportional to the digital input.
This is particularly useful for closed-loop applications.
C program
A simple C-language program (given at the end of this article) is used to calibrate and test the circuit after it is connected to the parallel port (LPT1) of the computer.
The program has two modes of operation, namely, automatic and manual.
In the automatic mode, a series of digi-tal values that start from 0 and increase until the value reaches 255 and then re-duce once again to reach 0, is sent to the port. This produces a dual-slope ramp that changes at the rate of 1 bit every 50 ms.
The load power increases linearly from 0% to a maximum of 100% and then reduces back to 0%.
In the manual mode, any value from 0 to 255 can be sent to the port. Sending a value of 255 results in maximum power (100%) to the load and sending a value of 0 results in minimum power (0%) to the load. Sending any other value results in a load power that is proportional to the in-put.
Calibration
The slope of the ramp generated is critical for proper operation of the circuit.
Fig. 3: Actual-size, single side PCB layout for proportional load control using PC Fig. 4: Component layout for the PCB
The slope is dependent on the capacitor’s charging current amplitude. This ampli-tude is fixed by resistor R7 and trimpot VR1. Because of component tolerances, the charging current cannot be set at the time of design. Improper setting of the current amplitude can result in unsatis-factory performance at the lower end of the input range.
After assembling the circuit, connect the D-type connector to the parallel port (LPT1). Set trimpot VR1 such that the resistance across VR1 is 0. Switch on the power to the circuit and run the C
pro-gram in manual mode. In this mode, a value of 0 has to be sent to the parallel port. Now increase VR1 until the voltage across the load crosses 0V. After calibra-tion, the circuit is ready to be used.
An actual-size, single-side PCB for the circuit is shown in Fig. 3 with its component layout in Fig. 4.
Cautions. 1. Use a low-tolerance polypropylene/polyester capacitor as C2.
2. Though the 100mA fuse (F1) is op-tional, connecting it will protect H11G1 in case the 47k resistor fails.
3. ICs must be handled carefully.
4. Using resistors with 1% tolerance for the R-2R ladder network improves lin-earity.
5. Any ‘sensitive gate’ triac can be used in place of BT139. The tab in BT139 is connected to MT2 and care must be taken to isolate this from the rest of the circuit.
6. Properly isolate the high side (the side connected to mains) of optocouplers H11G1 and MOC3022.
7. Don’t connect Analogue Ground (AG) and Digital Ground (GND) together.
/* Proportional Load Control */
#include <dos.h>
main() { int a,b,c,d;
int i=9;
clrscr();
printf(“\n\n\n\n\n\n\n”);
printf(“****** TEST PROGRAM *******\n”);
printf(“****** Written by Arvind S *******\n”);
printf(“**********************\n”);
printf(“****** Proportional Load *******\n”);
printf(“******* Control using PC *******\n”);
printf(“\n press any key to cotinued”);
getch();
while(i!=’0') { d=10;
clrscr();
printf(“Input Choice\n”);
printf(“Enter ‘1’ for Automatic testing, ‘2’ for manual testing\n”);
a=getch();
if (a==’1') { b=0;
while(b!=255) {
outportb(0x378,b);
b=b+1;
delay(50);
printf(“Sending Value %d to the port\n”,b);
} while(b!=0) {
outportb(0x378,b);
b=b-1;
delay(50);
printf(“Sending Value %d to the port\n”,b);
} } if (a==’2') { clrscr();
printf(“Type in Brightness value (0-255) and press Enter key\n”);
scanf(“%d”,&c);
printf(“\n Sending value %d to the port\n”,c);
outportb(0x378,c);
}
printf(“Type ‘0’ to quit, ‘9’ to continue\n”);
i=getch();
clrscr();
} }