store and output the stored code to enable in-situ coding and changing of the code easily. To retain the contents of RAM in case of power failure and to save power, a 4.5V battery backup arrangement is provided, so that the system may operate in power-down mode with the battery ca- tering to the retention of only the RAM’s contents. Thus, the power supply to the circuit can be switched off to minimise the power consumption to about 0.6 mA.
the Circuit
Memory organisation. A 6116 static
RAM (2048 x 8-bit) IC5 is used in the circuit with A9 and A10 address pins con- nected to the ground. Thus, here we are effectively using an address space of 512 locations only. This address space of 512 locations is further divided into 16 pages of 32 locations each. Page selection is done using 4-way DIP switch S2 in the circuit. Thus, in each page, an address space of 32 is available for storing the secret code.
Each digit of the code comprises a hex digit, which is stored as a nibble, requir- ing only 4-bit data space. It is stored as
16 pages randomly. For example, one can arrange to store an eight hex-digit secret code as first two digits in 1st page, next three digits in 8th page, next one digit in 3rd page, and the last two digits in 14th page.
SRAM 6116 is a volatile type memory. Therefore battery backup is required to retain data during power failures. The circuit around transistor T1, comprising diodes D1 through D4, resistors R4 and R5, capacitor C4, and a 4.5V battery pack connected to pins 24 and 18 of IC5 (SRAM 6116), allows the automatic changeover of the circuit to operate in power-down mode during power failures. In this mode, the static RAM chip retains data, while consuming very little power with as low a current as 0.03 mA to 0.6 mA—depend- ing upon the chip used. For example, HM611L-5 will draw 0.03 mA at 2V Vdd (in power-down mode), as per databook. This gives a long life to the battery.
Address counter. IC8 (74HC4040)
is a 12-stage binary counter, in which the five least significant address lines A0 through A4 (for addressing 32 locations) are sequentially selected on receipt of clock pulses. Selection for the required number of hex digits to be used as secret code can be made by jumpering one of the output pins (7, 6, 5, 3, or 2) of IC8 to pin 2 of IC9 (74LS32), using jumper JPN1 for obtaining 2-, 4-, 8-, 16-, or 32-hex digit long secret code, respectively.
Keyboard encoding. 16-key keyboard
encoder IC1 74C922 is used in conjunc- tion with a 16-digit keypad for encoding the pressed key data. It comprises an internal oscillator for clock generation for its own use and an inbuilt key debounce circuitry. Capacitors C2 and C3 connected be up to 32 hex digits. One can, however,
keep one’s secret code spread over all the
PArts List
Semiconductors:
IC1 - 74C922 hexadecimal key- board encoder
IC2 - 74HC244 octal tri-state buffer IC3 - 74HC688 8-bit comparator IC4, IC7 - 74HC132 quad 2-input
NAND gate with Schmitt trigger input
IC5 - 6116 2k x 8-bit SRAM IC6, IC8 - 74HC4040 12-stage binary
counter
IC9 - 74LS32 quad 2-input OR gate IC10 - 74LS74 dual J-K Flip-Flop IC11 - 7805 regulator 5V T1 - BS170 n-channel MOSFET T2 - BC548B npn transistor D1, D2, D5 - 1N4148 switching diode D3, D4 - 5.1V, 0.25W zener diode D6 - 1N4001 rectifier diode D7, D8 - 1N4007 rectifier diode
LED1 - Red LED
LED2 - Yellow LED
LED3 - Green LED
Capacitors: C1, C3 - 1µF, 10V tantalum C2 - 100nF ceramic disk C4 - 470nF ceramic disk C5 - 10µF, 10V electrolytic C6 - 2200µF, 25V electrolytic C7 - 100nF, ceramic disk
Resistors (all ¼-watt, ±5% carbon, unless stated otherwise): R1 - 100-kilo-ohm R2, R3, R5, R7, R10, R11 - 10-kilo-ohm R4 - 1.5-kilo-ohm R6, R8, R9 - 470-ohm R12 - 27-ohm R13 - 2.7-kilo-ohm
RN1 - 4x10-kilo-ohm resistor net- work (5-pin SIP)
Miscellaneous:
RL1 - 12V, 500-ohm relay, PCB mountable
S1 - SPDT switch
S2 - 4-way DIP switch S3 - Push-to-on switch
through resistor R2 to keep this chip in enabled state. The DA out- put signal at its pin 12 is used for the following func- tions via the gates of quad NAND Schmitt IC4 and IC7:
(a) As a clock for 12-stage bi- nary counter IC8 (74HC4040) via Schmitt NAND gates N1 and N8, which advances the counter by one count for every clock.
(b) For sound- ing of buzzer BZ1 and lighting of LED1 via Sch- mitt NAND gates N7, N5, and N6 to provide audio- visual indication to the effect that t h e d a t a c o r - r e s p o n d i n g t o the pressed key has been gener- ated for further processing.
A u t o - r e s e t c i r c u i t . I C 9
(74LS32) is a q u a d 2 - i n p u t OR- gate chip, of which only one gate is used here. This gate is wired as a reset circuit (both for auto and manual reset op- eration) for IC8 and IC6. One can reset both the counters (IC6 and IC8) manually, by pressing reset switch S3.
A u t o - r e s e t function will take place whenever preset number of digits of secret code has been entered, either for verification/ operation or for registration. In verifica- tion mode, the secret code would either a pressed key. Whenever a key is pressed,
DA (data available) output pin 12 goes to logic 1, to indicate availability of fresh data at its output pins (14 through 17).
This pin 12 reverts to its logic low state when the pressed key is released. The data outputs of IC1 are tri-state. Its output enable (OE) pin 13 is grounded
Fig . 1: Schematic diagr am of v ersatile digital c ode lo ck
be right or wrong. Basically, the auto- reset function keeps the secret code really secret, and is smart enough to confuse an intruder.