circuits presented in EFY so far had been based on discrete TTL and/or CMOS ICs. This circuit is based on a familiar EPROM 27C32, wherein the required code is stored. It is a number lock, which can be programmed to any coded number. The length of the number can also vary.
To make a code-lock for a particular number (octal, decimal, or hexadecimal),
loaded with binary byte XXXXXXX0 (here, X means “do not care”). The data is stored in consecutive locations, starting with location 001H, as stated earlier.
description
The circuit comprises six ICs, inclu- ding the EPROM and the voltage regu- lator. IC1 is a timer NE555, which is configured as a monostable flip-flop. Please note that its reset pin 4 is connected to output A = B (OA=B) pin 3 of comparator IC4 (CD4585). Thus, as long as 4-bit magnitude of input A to IC4 is equal to 4-bit magnitude of the other input B (to IC4), its output pin 3 is at logic 1 and thus monostable IC1 is enabled. When magnitude of input A is not equal to B, the output pin 3 of IC4 is at logic 0 and as a result IC1 is disabled.
In enabled state, the monostable IC1 generates an output p u l s e w h e n s w i t c h S1 (marked zero) is momentarily pressed. This output pulse from IC1 is used as a clock pulse for counter IC2 that number is first converted to its
binary equivalent. It is then entered bit- by-bit into consecutive memory locations of EPROM 2732 (IC3), starting with the MSB and ending with the LSB (D0). Assume that the required number is 12 (hex). Its equivalent binary number is 00010010. This binary number is entered into the EPROM at memory locations starting with 001(hex), as shown in Table I. The first memory location is always
going transition of the clock. Hence, to synchronise the operation of IC2 and IC5, the clock pulse to IC2 is inverted by the transistorised inverter stage around transistor T1.
At power on, IC2 is reset due to power-on-reset circuit built using ca- pacitor C3 and resistor R5. Hence, all its outputs (including O0 through O5 connected to addresses A0 through A5 of EPROM IC3) are initially at logic 0. In other words, initial ad- dress selection for EPROM is 000H, since address lines A6 through A11 of EPROM 27C32 are permanently grounded in this circuit. With each clock pulse from IC1, the counter IC2 output increments by one and so also the address of EPROM. Since the clock pulses from IC1 are also being applied
Fig. 2: Acutal-size, single-sided PCB layout
Fig. 3: Component layout for the PCB
PaRtS liSt
Semiconductors:
IC1 - NE 555 timer
IC2 - CD 4040 12-bit binary counter
IC3 - 27C32 EPROM
IC4 - CD 4585 4-bit magnitude comparator
IC5 - CD 4035 4-bit shift register
IC6 - 7805 regulator
T1, T2 - BC 547 npn transistor
Resistors (all ¼-watt, ±5% carbon, unless stated otherwise): R1, R5 - 10-kilo-ohm R2 - 220-kilo-ohm R3 - 2.2-kilo-ohm R4 - 3.3-kilo-ohm R6 - 15-kilo-ohm R7, R8 - 1-kilo-ohm Capacitors: C1 - 1µ/10V electrolytic C2, C4 - 0.01µ ceramic disk C3 - 10µ/10V electrolytic C5 - 22µ/10V electrolytic C6 - 1000µ/16V electrolytic Miscellaneous: RL1 - 6V/100-ohm relay S1, S2 - tactile switch S3 - On/off switch - DC power supply (7.5V to 12V) to clock pin 6 of 4-bit shift regis- ter IC5 (CD4035), let us examine h o w t h e d a t a at its input pins 3, 4 (K, J) and output pin 1 (O0) changes. Please note that O1 through O3 (at pins 15, 14 and 13 respectively) of the shift register are not used in this circuit.
O n i n i t i a l switching ‘on’ of power supply to the circuit, IC5 is reset due to the power-on reset circuit com- prising capacitor C5 and resistor R6, connected to its master reset pin 5. Thus, initially its output O0 at pin 1 is at logic 0. On receipt of first clock pulse from IC1, the data pin states of J and K pins (4 and 3) get shifted to output pin 1. The logic level at these two pins (3 and 4) is normally zero as they are pulled to ground
via resistor R3, when push to ‘on’ switch is in its normal (off) position. However, if switch S2 is kept pressed when clock pulse is generated by IC1 (by pressing switch S1 momentarily), logic 1 is output to pin 1 of shift register IC5.
In this circuit, the final opening or closing of lock is achieved through en- ergisation of relay RL1 via relay-driver transistor T1, whose base is connected to either O2, O3, O4, or O5 outputs of IC2 via resistor R7. The selection of the position where point A is to be connected would depend on the binary digits in the code. If binary code is of 4-bit length (equivalent to one hex digit), then four clock pulses are needed for advancing the EPROM address by four locations. On fourth pulse, O2 will be at logic 1 (unless IC1 gets disabled due to non-matching of the code in comparator CD4585, earlier) to energise relay RL1. For 8-bit long code (equivalent to two hex digits), the tap A
needs to be connected to O3. Similarly, for 16-bit code, point A is to be connected to O4, and so on.
operation
When the power supply to the circuit is initially switched ‘on’, IC2 and IC5 are reset, as explained earlier. Both A0 and B0 inputs to IC4 are zero and thus its output at pin 3 is ‘high’ and hence IC1 is enabled. But, since pin 2 of IC1 is pulled ‘high’ via resistor R1, output of IC1 is initially ‘low’. Initially, all ICs are in their reset positions because of the capacitors connected to their reset pins.
Assume that the required code number is lodged in the EPROM and point A is joined to appropriate output of IC2 depending on the length of lodged code, as discussed in the description of relay operation. Then, lock relay can be energised by inputting the correct binary code serially via IC5 TABLE I
Memory address Data (Hex) Hex Binary
equivalent 000 X0 XXXXXXX0 001 X0 XXXXXXX0 002 X0 XXXXXXX0 003 X0 XXXXXXX0 004 X1 XXXXXXX1 005 X0 XXXXXXX0 006 X0 XXXXXXX0 007 X1 XXXXXXX1 008 X0 XXXXXXX0
with the help of switches S1 (marked zero) and S2 (marked one). A ‘zero’ is entered by momentarily depressing switch S1 alone, and a ‘one’ is entered by depressing switch S1 momentarily, after holding switch S2 in the pressed condition.
The ‘D0’ bit of EPROM and ‘O0’ bit of shift register (CD4035) are compared by magnitude comparator (CD4585). If the two data bits are equal, the output of compara- tor remains ‘high’ and it does not interrupt/ inhibit the operation of monostable IC1 (NE555). However, if there is a mismatch, the output of comparator goes ‘low’ and it
inhibits IC1. Thus, further data would not get entered in the absence of clock pulse from IC1. If data at each location of EPROM keeps matching with the data input via switches S1 and S2, the output of compara- tor (at pin 3) will continue to stay ‘high’ to keep IC1 enabled until all the bits of the code have thus been compared. At the end of the code, the tap A will be at logic 1, to energise relay RL1. If you have by mistake entered wrong code via switches S1 and S2, you can try again by switching ‘off’ and then switching ‘on’ the circuit once again, using ‘on’/‘off’ switch S3.
Please note that for locking, the cir- cuit need not play any role. The locking operation could be performed manually. Only for opening of the lock, this code lock may be used. However, you are at liberty to use the lock the other way around.
An actual-size, single-sided PCB for the circuit of Fig. 1 is shown in Fig. 2, while Fig. 3 shows its component layout. One may extend/modify the circuit by utilising other seven unused data bits of EPROM as well (presently only bit D0 has been used in this circuit). ❏