T
he 8051 microcontroller, first de- veloped by Intel, finds many ap- plications in small development systems such as speed control of DC motors, timers, process-control applica- tions, and temperature controllers. One of its simple applications as multi-effect chaser lights is described in this project.Here the microcontroller 8051 controls the switching sequence of eight triacs (TR1 through TR8) via the buffer transistors T1 through T8, as shown in the schematic diagram of Fig. 1. Each triac, in turn, may be used to control a series of bulbs (with a total voltage drop of 230V AC and the current drawn through BT136 triacs not exceeding 4 amp).
Features of 8051 micro-controller.
The heart of the circuit is the 8051 micro- controller. Some of the important features of the controller are as follows:
— 8-bit CPU with register A (accumu- lator) and register B.
— 16-bit program counter (PC). — 16-bit data pointer (DPTR). — 8-bit program status word (PSW). — 8-bit stack pointer.
— 128 bytes of internal RAM. — No ROM for 8031, 4k ROM for 8051, and 4k EPROM for 8751.
— Two external and three internal interrupt sources.
— Four programmable input-output ports/registers.
One of the important parts of the 8051 CPU is its oscillator section. The oscilla- tor section is present on the chip itself, only quartz crystal has to be connected externally between pins 18 and 19. The crystal frequency should range between 1 MHz and 16 MHz for proper function-
PARTS LIST
Semiconductors:
IC1 - 8051 microcontroller IC2 - 74373 octal ‘D’ type latch-
es
IC3 - 2764 EPROM 8-kbytes
IC4 - 7805 regulator +5V T1-T8 - BC547 npn transistors TR1-TR8 - BT 136, triac LED1-LED8 - Red LED
Resistors (all ¼-watt, ±5% carbon, unless stated otherwise): R1-R16 - 560-ohm R17 - 47-ohm R18 - 10-kilo-ohm Capacitors: C1, C2 - 30pF ceramic disk C3 - 100µF, 16V electrolytic C4, C5 - 10µF, 25V electrolytic Miscellaneous:
XTAL - 12MHz quartz crystal
L1-L8 - L1 through L8 could each be a series of bulbs with total voltage-drop of 230V AC - Heat-sink
S1 - Push-to-on switch
ing of the controller. If this frequency is taken below 1 MHz, there is a chance of losing data of its internal RAM.
Pin 31 happens to be the external access pin for the controller. If this par- ticular pin is grounded, 8051 fetches program from the externally connected ROM/EPROM. And if it is connected to Vcc, it starts executing the program from the internal ROM that has 4k address space (0000H-0FFFH). For 8031, there is no internal ROM present, and hence this pin has to be grounded for its proper operation.
When internal ROM is used, and if the program exceeds the 4k internal ROM address space, then after the last address 0FFFH, it starts executing the program
from externally connected ROM/EPROM. The externally connected ROM/EPROM can be increased up to 64k, i.e. 0000H- FFFFH. In the case of RAM, the same can be extended up to 64k.
It should be noted that the 8051 is organised such that data memory and program memory can be two entirely dif- ferent physical memory entities. Another important aspect to be discussed relates to its input-output (I/O) ports. The 8051 has a total of four 8-bit ports, namely, P0, P1, P2, and P3.
P0. The P0 port may be used as input,
output, or as combined low-order address and a bidirectional data bus for external memory, which is an alternate function.
P1. Port P1 does not have any alter-
nate function. It means that these pins are used for interfacing input-output devices like ADC, DAC, 7-segment displays, LCD, keyboard, etc.
P2. Port P2 happens to be the high-
order address lines, i.e. A8-A15. This port can be used for interfacing I/O devices. It should be noted that port 2 is changed momentarily by the address signals when supplying the byte of a 16-bit address.
P3. Port 3 functions in a fashion simi-
lar to that of port 1. Each pin of port P3 performs different operations as shown in Table I.
Hardware
The controller is interfaced with the external memory (EPROM) via the octal ‘D’ latch 74LS373. The purpose of using 74LS373 is to de-multiplex the address lines and the data lines. Hence, after de-
multiplexing, AD0-AD7 forms two sets of lines—address lines A0-A7 and data
memory address and then the same port acts as bidirec- tional data bus to read a byte of memory, whereas port P2 provides the higher byte of memory address during the read cycle. It is further seen that the lower-order address byte of port P0 gets latched into external register of 74373 (IC2) to save the particular byte. The ALE
low and enables the EPROM to output the code on the data bus. The purpose of using PSEN (program store enable) is that it provides the output signal for the program m e m o r y / c o d e memory. When this signal goes low, controller can read instruction byte from the pro- gram memory. U n d e r t h e program control, 8051 provides the output to port P1, which is further cou- pled to the base of driver transis- tors T1 through T8 (BC547). A logic 1 at any of the output pins of port P1 will drive the corre- sponding LED as well as the gate of the triac. The cor- responding triac therefore fires to drive the lamp/ lamps connected between its ter- minal A2 and the neutral line (N). If you use, say, 12V lamps, you may connect about 20 lamps in series. If each lamp is of 25-watt (passes about 2A current) rating, you may connect two rows of 20 such bulbs across A2 terminal of each triac and neutral line. The soft- ware program determines the triggering sequence of the triacs to provide the light- ing effects.
software
As mentioned earlier, lighting of bulbs is
Fig. 1: Schematic diagram of multi-effect chaser lights
TAbLe I
Pins Use
P3.0 (RXD) Receive data serially
P3.1 (TXD) Transmit data serially
P3.2 (INT0) External interrupt zero
P3.3 (INT1) External interrupt one
P3.4 (T0) I/P pin for timer 0
P3.5 (T1) I/P pin for timer1
P3.6 (WR) External memory write pulse
into the accumulator one by one and will get transferred to port P1. If the format of these codes or their sequence is changed, the output too will get altered in same manner. Please note that outputting logic 1 from any pin (equivalent to setting a specific bit) will switch ‘on’ the corresponding triac (and the series of bulbs connected across its terminals A2 and N), whereas output- ting logic 0 from the same pin of port P1 (equivalent to clearing/ resetting the specific bit) will switch it ‘off’. The output code format from port P1 is shown in Fig. 4.
Example 1: If there is a requirement to set only P1.0 bit, the out- put format from port P1 will be as shown in Fig. 5.
For converting the above format to normal hex level, you have to apply 8421 logic (Fig. 6) and you get 01H.
Example 2: To set P1.0 and P1.7, you have to output 81H from port P1 (Fig. 7).
In the software program, total codes to be displayed are 0 0 7 C H – 0 0 2 3 H = 0059H, as mentioned earlier, and hence 59H is loaded in the main program at memory location 0012H. Fur- ther, register R3 be- ing an 8-bit register, the maximum count is restricted to FFH (255 decimal). Since we are comparing the contents of register R3 with 59H, when regis-
ter R3 reaches that count, the compare instruction gets satisfied and it jumps to label 2 (in the program). In case you wish to extend the codes to be out-
Fig. 2: PCB layout for the circuit
Fig. 3: Component layout for the PCB
put from port P1, the loaded count at memory location 0012H has to be al- tered correspondingly. The program, when run, produces an eye-catching
Fig. 4: Output code format from port P1
Fig. 5: Output code format for setting only P1.0
Fig. 6: Hex code for Fig. 3
Fig. 7: Hex code for setting P1.0 and P1.7 bit
lighting effect. The complete program listing (CHASER. LST) is given in the box ahead.
An actual-size, single-sided PCB for the circuit in Fig. 1 is shown in Fig. 2 and its component layout is shown in Fig. 3. It is im- portant that neutral and phase (live) lines of 2 3 0 V A C a r e n o t interchanged, because only the neutral line is required to be ground- ed to PCB common ground and not the live line.
003F 01 DB 01H 0040 11 DB 11H 0041 22 DB 22H 0042 44 DB 44H 0043 88 DB 88H 0044 44 DB 44H 0045 22 DB 22H 0046 11 DB 11H 0047 33 DB 33H 0048 77 DB 77H 0049 FF DB FFH 004A 77 DB 77H 004B 33 DB 33H 004C 11 DB 11H 004D 81 DB 81H 004E 42 DB 42H 004F 24 DB 24H 0050 18 DB 18H 0051 24 DB 24H 0052 42 DB 42H 0053 81 DB 81H 0054 C3 DB C3H 0055 E7 DB E7H 0056 FF DB FFH 0057 E7 DB E7H 0058 C3 DB C3H 0059 81 DB 81H 005A 01 DB 01H 005B 02 DB 02H 005C 04 DB 04H 005D 08 DB 08H 005E 10 DB 10H 005F 20 DB 20H 0060 40 DB 40H 0061 80 DB 80H 0062 40 DB 40H 0063 20 DB 20H 0064 10 DB 10H 0065 08 DB 08H 0066 04 DB 04H 0067 02 DB 02H 0068 01 DB 01H 0069 03 DB 03H 006A 0C DB 0CH 006B 30 DB 30H 006C C0 DB C0H 006D 30 DB 30H 006E 0C DB 0CH 006F 03 DB 03H 0070 0F DB 0FH 0071 F0 DB F0H 0072 FF DB FFH 0073 00 DB 00H 0074 FF DB FFH 0075 00 DB 00H 0076 FF DB FFH 0077 AA DB AAH 0078 55 DB 55H 0079 AA DB AAH 007A 55 DB 55H 007B AA DB AAH 007C 55 DB 55H ❏
Add. Code Label Mnemonics Comments
ORG 0000H ;ROM starting address 0000 E4 CLR A ;Clear contents of accumulator 0001 759000 MOV P1,#00H ;Clear port 1 (off all LEDs) 0004 900023 MOV DPTR,#0023H ;Moving immediate DPTR
;with 0023 (starting address of ;O/P codes)
0007 7B00 LABEL2: MOV R3,#00H ;Clearing the contents of register R3
0009 E4 LABEL1: CLR A ;Clear accumulator 000A 2B ADD A,R3 ;Adding the contents of
;accumulator and register R3 000B 0B INC R3 ;Incrementing the contents of
;register R3 by 1
000C 93 MOVC A,@A+DPTR ;Copy the code byte, found at ;ROM address formed by add- ing ;A dn the DPTR, to A 000D F590 MOV P1,A ;Move the content the contents
;of accumulator to port 1 000F 1116 ACALL DELAY ;Calling delay
0011 BB59F5 CJNE R3,#59H, ;compare the contents of regis- LABEL1 ;ter R3 with 59H and jump
to ;labell if not equal else continue
0014 80F1 SJMP LABEL2 ;Short jump to label2 0016 7801 DELAY: MOV R0,#01H ;Move immediate register R0
;with 01H
0018 7900 LABEL5:MOV R1,#00H ;Move immediate register R1 ;with 00H
001A 7A00 LABEL4:MOV R2,#00 ;Move immediate register R2 ;with 00H
001C DAFE LABEL3:DJNZ R2,LABEL3 ;Decrement the content of ;register R2 till it becomes zero 001E D9FA DJNZ R1,LABEL4 ;Decrement R1 till zero 0020 D8F6 DJNZ R0,LABEL5 ;Decrement R0 till zero
0022 22 RET ;Return
0023 01 DB 01H ;DB(Define Byte) is 0024 02 DB 02H ;the assembler directive
0025 04 DB 04H 0026 08 DB 08H 0027 10 DB 10H 0028 20 DB 20H 0029 40 DB 40H 002A 80 DB 80H 002B 40 DB 40H 002C 20 DB 20H 002D 10 DB 10H 002E 08 DB 08H 002F 04 DB 04H 0030 02 DB 02H 0031 01 DB 01H 0032 03 DB 03H 0033 07 DB 07H 0034 0F DB 0FH 0035 1F DB 1FH 0036 3F DB 3FH 0037 7F DB 7FH 0038 FF DB FFH 0039 7F DB 7FH 003A 3F DB 3FH 003B 1F DB 1FH 003C 0F DB 0FH 003D 07 DB 07H 003E 03 DB 03H
Add. Code Label Mnemonics Comments
ElEctronic BEll SyStEm
Dr D.K. KaushiK
I
n this innovative project, a simple electronic bell system using com- monly available ICs is presented for use in educational institutes. This simple and easy-to-fabricate project has the fol- lowing features:• It sounds the bell automatically after every period of 40 minutes.
• It displays in digital form the cur- rent time and period number of the class going on.
• The system automatically switches off after the last period (11th period). The digital clock showing the current time,
wattage may be used for the bell. In the prototype, the author used an audio tape recorded with the usual sound of brass bell, with tape recorder/player of 150 watts rating, driving four 20-watt speaker units. It is considered adequate for the campus of any educational institute. The readers may, however, use any other sound system according to their requirements.
Part III consists of the period counter and display. It displays the current period in progress. The number of pulses received at 40-minute intervals are counted by this counter circuit and the display unit displays the period number.
One additional relay circuit is used so that the power supply given to parts II and III of the system is automatically interrupted at the end of the eleventh however, continues working as usual.