Clock And Clock_Bar

The clock and clock_bar signals are generated from the single-ended +1V supply, using a cascade of level shifting inverters and regular inverters (INTs). The level shifting inverter has a 2.5V MOSFET device, as the voltage across it can be as high as 2V, for low logic input from the WFGINT of the Schmitt Trigger. It is worth noting, that series inverters are not required to sharpen the WFGINT output signal, since the square output signal has no distortion [54, 194]. The symmetrical behaviour of the INVs is achieved by sizing the PMOS (MINVP) width larger than NMOS (MINVN) width; since the NMOS mobility is larger than that of PMOS, the actual sizes are extracted by means of simulations. An iterative simulation was applied to optimize the INV size, and a symmetrical output waveform is obtained by using the same channel length and by sizing the PMOS width Wp = 6μm, three times the NMOS width, WN =2μm, for both inverters. Figure 4.14 shows the simulated transient response of the clk and clk_bar signals which are of rail-to-rail signal swing with frequency of 17kHz. By considering the number of MOSFET transistors as a rough metric of the layout area, given that minimizing the width of MOSFET transistors was one of the main goals, this gives the total active area for the clk and clk_bar of ∑WNINV L= 1.92μm2_.

140 4.6.2 FD circuit

The FD circuit also utilizes a +1V supply and its critical delay path was scaled for satisfactory performance. Power consumption as well as silicon area of the FD circuit depends on appropriate Flip-flop topology and the device W/L ratios.All of the TGMS D-FFs utilized were identical copies. To optimize the FD, the circuit was investigated for various widths of the NMOS and PMOS devices for both the INV and TG elements using the same actual channel length. Accordingly, an iterative process was employed to optimize all the FF stages for a low power budget. Initially, all transistors were sized for minimum size (0.36μm) and sized up iteratively for precise functionality. By varying the WTGP,N of the TG with respect to WINVP,N (smaller, equal, or larger than the width in the INV). Considering minimum value Wmin, it was found that a symmetrical and accurate functionality is obtained by sizing the WINVP=6μm three times, WINVN =2μm, while the WTGP and WTGN of the TG are sized to equally: WTGP = WTGN = 2.5WINVN =5μm. The active area for each FF was ΣWINV L + ΣWTG L =4.32μm2_, where Ʃ WINV .L is the sum of the areas of all the inverter devices and ΣWTG L is the sum of the areas of all the TG devices. The overall active area of the 16 TGMS D-FFs is then equal to 138.24 μm2_{. The inverter sizing for MUX, PS and the output stage were the} same as that of the clk, while NMOS and PMOS of the TG for the MUX circuit are sized, based on the standard approach, to have equal size; WP and WN are then varied through a wide range. The optimal W for each combination of the TG is achieved by setting the WTGP = WTGN =5μm, which is the same as for D-FF circuit. The total active area for the two MUXs was ΣWTG L+ ΣWINV L = 39.36μm2_{, while the total active area} for the PS and the output stage was ΣWTG L +Σ WINV L= 4.32μm2_{.The total active area} of the digital block (including INV) was approximately 183.84μm2_{. Figure 4.15 shows} the 16 channel output square waveforms digitally selectable through MUX1, MUX2 and PS. For a general design requirement, and since the power dissipation of the designed digital circuit is dominated by the FD circuit, the low-power design goal of the FD circuit becomes the task of minimizing, while remembering the precise functionality and identifying the trade-off of such minimizations in terms of performance and area. Since the FD circuit is relatively simple and symmetrical it was easy to express all transistor widths as a function of one variable WN (WP = 3WN for INV and WTG = 2.5WN for TG) for the purpose of optimization.

141

Figure 4.15. The 16 channel output square waveforms digitally selectable through MUX1, MUX2 and PS.

142

The optimum FD device-width WN vs. power and area was then determined through simulations. Table 4.1 summarizes these results. Regarding sizing, the data reported in Table 4.1 considered the final iterative result of the FD transistors only, without the contribution of all iterative process. Hence WN, WP and WTG are the weight factors for area and power consumption. The optimal design was achieved by constraining these weight factors without impairing circuit performance. In terms of area consumption, obviously a circuit with small W consumes a small silicon area, while using small W can also reduce power consumption, but the circuit may not function properly. Figure 4.16 shows the proportionality relationship between power consumption and WN. However, values of W that are too small lead to increase in the effective switching resistance of the logic gate and decrease the inverter gain. Consequently, for optimum operation and to improve the inverter gain, slightly oversize WN was chosen. A high gain logic gate also enhances the resolution of any metastability in the logic signals [200]. The effect of supply-voltage scaling on the power dissipation of the FD circuit was also investigated. To evaluate low-power performance, the supply- voltage is varied from 0.6V to 1.2V yielding the power and frequency variations shown in Figure 4.17 and Figure 4.18 respectively. The FD circuit dissipates 0.45mW at input frequency of 10.3kHz with VDD = 0.6V, 1.1mW at input frequency of 13.5kHz with VDD = 0.8V, 2.1mW at input frequency of 17kHz with VDD =1V and, 3.6mW at input frequency of 20kHz with VDD = 1.2V. The input frequency is the WFGINT frequency at a particular supply-voltage. Figure 4.19 shows the simulated speed (WFGINT frequency)-power trade-off of the FD circuit. The symbol ‟□” represents the point of the best (optimal) power and accurate functionality trade-off. Using VDD of +1V indicates acceptable power-frequency trade-off. The simulation results thus indicate that the designed WFGINT core is able to generate up to 17kHz with a power consumption of only 0.457mW (using ±1V), while the FD circuit consumes 2.1mW (using +1V), resulting in total power dissipation of only 2.557mW.

The effect of the tuning range (using V_tune) of the gm-C integrator on the overall power dissipation of the proposed circuit with C=10pF was also investigated. Figure 4.20 displays the result for frequency and power vs. V_tune varied in the range ±0.9V. The proposed circuit dissipates 2.5mW at 5.8kHz (with V_tune = – 0.9) and 5.8mW at a high frequency of 1003kHz (with V_tune = 0.9). The optimal transistor dimensions and passive component values for the proposed analog WFGING are

143

displayed in Figure 4.2, while, for the FD WN=2μm (so that, WP=6μm and WTG=5μm) was chosen with L=130-nm. For the TG, PMOS and NMOS devices have same device- size and hence identical layout geometry. The optimal performance of the system is presented in Table 4.2.

Table 4.1. The power and area versus generalized transistor width for the designed FD circuit.

144

Figure 4.17. Power dissipation versus supply voltage of the FD circuit.

145

Figure 4.19.The simulated speed-power trade-off of the FD circuit.

146

Table 4.2. Simulation results of the outputs of the dual band WFGINT designed circuit.

4.7 Layout and Fabrication of The WFG

The layout of the designed circuit, has been implemented in 130-nm IBM (now GF) CMOS process technology on Mentor Graphics Pyxis CAD programme and were verified to function correctly. In order to optimize the layout for size, the proposed circuit is implemented, using full-custom design techniques utilizing MOSFETs at the lowest level with high regularity. To minimize the layout area of the designed circuit, the same layout procedure adopted in section (3.7) is applied. Considering the design rules, all routing was completed manually with verifying DRC. Each NMOS and PMOS device in analog and digital models is implemented individually with small layout area, and they are connected with a constant height. So, horizontal runs of metal are applied to provide VDD, VSS and ground to the devices, which saves silicon area. The same rules are also used for the substrate and well. The importance of this is that power and ground, as well as substrate and well, are easily routed, with the ordinary arrangement of each device. The DRC and LVS checks were performed for each completed sub-cell and were passed. The active chip area of the complete circuit was 18426μm2 (including

all interconnects). The analog WFGINT including clk and clk_bar (excluding the capacitor) occupied a small chip-area of 640μm2, and the on-chip capacitor of 10pF

Parameters WFGINT Digital model

Lmin 0.24nm CMOS 0.13nm CMOS

Amplitude 1.5 Vpp 1Vpp Core Frequency 17 kHz 17 kHz Duty cycle 50 % 50 % Output current i IPP =164 μA source Period 58ns Slew rate 2.6 GV/ns Supply voltage ±1 V +1 V Power consumption 0.457mW 2.1mW Total active area 67.08μm2 _183.84μm2