Frequency Tuning Range
4.3 Circuit Design and Topology of The WFG INT
4.3.5 Components Sizing for Low Power & Low Frequency WFGINT Design For an appropriate low frequency design and to reduce power consumption and
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Considering the differential pair M1, M2 in STG1 having the same small signal parameters, gm1= gm2 and ro being the output resistance, the loop gain of the core oscillator can be given by,
= , ∙ // ∙ ∙ ∙ ∙ // (4.27)
Where, gm1, gm2, gm5 and gm6 are the trans-conductance of M1, M2, M5 and M6 in the linear amplification range. By substituting the expressions for gm and
, in equations
(3.2) and (3.3) respectively, and λ ⍺ (1/ ), then the proportionality can be determined betweenloop gain , the controllable variable(W/L) and the drain current (ID) whichcan be then given by,
⍺
, ∙ , ,∙
∙∙
∙( ∙ )(4.28)
Since ⍺ ( . ) / , equation (4.28) shows that the open-loop gain goes up by increasing the square root of WxL, and also by reducing the drain current . Using small DC drain bias current also significantly improves power consumption. Hence bias current sources M12, M13 and M14 are designed to have very high output impedance roN, and in relation to this design, the values for L12, L13 and L14 should be made 2 times longer than the minimum length. The maximum output swing for the circuit, being near the positive supply voltage ( =VDD), is limited by M6 going into the triode region, being ON as switch with very small drain-to-source drop. M6 thus requires a very small RDS (ON) using a reasonably wide PMOS device. The minimum output value ( = –IB3R) is limited by the gate voltage of M14 and the regenerative positive feedback resistor R. Basically to bring the minimum output value closer to the negative supply voltage, the drain voltage VD14 of M14 may not go below the gate voltage of M14 by more than VTHN, hence,
= + − (4.29) Substituting for VGS14 – VTHN gives,
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=
+
(4.30)
Hence, to improve the swing, the value of VGS14 must be made small, resulting in large values of W14/L14. Using an appropriate resistor R can also enhance the output swing. However, more important in the circuit design are the sizes of M1 and M2 are which dominate overall circuit performance. For proper operation of the three stage operational amplifier of the Schmitt Trigger, the gate potential at the inputs Vin1+ and Vin2- of STG1 should be within a limited range. If the input voltage goes beyond this range, the operational amplifier gain drops and the WFGINT circuit cannot function properly. The maximum input VG1,2(MAX) is limited by both M1 and M2 going into the triode region, and hence, VG1,2(MAX) = VDD -|VGS3| + VTHN. Substituting for VGS3, the maximum input for M1 and M2 can be given by,
, ( ) = − + + (4.31)
Where, |VGS3| is written in terms of its drain current ID3=IB1. The minimum input voltage VG1,2(MIM) is limited by M12 driven near the edge of saturation, hence, VG 1,2 (MIN) = VSS +|VDS12| + VGS1,2. Since the overdrive VOD12 ≈ VDS12,
≈ = − (4.32) So, , ( ) = + + , , (4.33)
Equations (4.31and (4.33) show the variables for improving VG1,2(MAX) and VG1,2 (MIM) of the pair M1, M2 of STG1. To make VG1,2(MAX) as large as possible, IB1 and L3 should be made as small as possible, while W3 is made as large as possible, on the other hand, to
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make VG1,2(MIM) as small as possible, L12, IB1, and L1,2 should be made as small as possible, while increasing W12 and W1,2 as much as possible.
The oscillation frequency of the designed WFGINT is set by the time constant of the gm-C integrator. Thus, the design parameter of the gm-C integrator is also important. Since ⍺ ( , . )/ , ) , (equation 4.13) hence, for small gm7,8 value design, (assuming small C value), the decreases as the W7,8 and DC drain biasing current IB4 reduce, while L7,8 increases. Making W7,8 small is in direct conflict with its open loop gain ⍺ , ∙ , / , . Thus W7,8 presents tradeoffs
between the gain and the frequency, such that, by increasing the width of the differential input pair M7-M8, although the gain goes up (by the square root of W7,8) the frequency is also increased by the square root of W7,8. If the width W7,8 is narrower, then the gm7,8 and, hence, the frequency are reduced. Therefore, by choosing a reasonable W7,8, a relatively a long channel length L7,8, by about 2-5 times the minimum length, the frequency of the designed circuit decreases and the integrator open-loop gain increases. Thus, the trade-off between and, may be eliminated by controlling the C value. The value of C can be approximately determined from the bandwidth specification in (4.13) by iteratively selecting W7,8, L7,8 and IB4 values and solving for C. A high–impedance node usually has a low frequency pole associated that reduces the speed of the amplifier. Since the frequency response of the integrator will be dominated by the high impedance nodes ( // ) (equation 4.5) and the load capacitor C, for low frequency integrator design and low capacitor load value, M8 and M10 are assumed to have high output impedance; relative to the impedance, the values for L8 and L10 should made at least 2 times longer than the minimum length. The gm7,8 value, and hence, the frequency of the circuit can also be reduced by simply reducing the biasing current IB4. The small current IB4 can also enhance the gm-C DC gain. This result shows that using a small DC basic current, the lowest oscillation frequency value and largest possible voltage gain can be achieved with small capacitor value. Also, using a small DC drain biasing current, a large frequency tuning range with adequate linear range can be achieved, significantly reducing power consumption, as per (2.7). However, gm7,8 will be a design parameter in the WFGINT based integrator relaxation timing network much as are resistors and capacitors in a ELF WFG based RC relaxation timing network.
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From the above analysis, it can be concluded that for high gain, low speed with reasonably linear output range, trade-offs must be considered, as the designer selects a circuit topology and begins the simulation process of iterating a final design with possible set of W, L, IB and C. Hence, the low frequency WFGINT can be implemented fully on chip, with significantly reduced power consumption and silicon area.