A thorough analysis of the IteRX design has been carried out throughout this chap- ter. A consistent comparison to other similar implementations is unfortunately not possible due to several reasons. First of all, only one other MIMO IDD silicon im- plementation has been reported in the literature so far, to the best of the author’s knowledge. However, the data provided by [116] is limited to a few operating points and relates to the single PEs, rather than the joint baseband processing. Therefore, this design could only be compared to the IteRX chip in terms of peak efficiency, as shown in Section 4.4.
Similarly, a number of complete non-iterative MIMO receivers are reported in the literature (a fairly exhaustive list can be found in [169]). However, the implementation results are given either for the complete baseband and RF (if included) as a whole or for the single isolated components (e.g., in [168]), making a consistent comparison with the results presented in this thesis problematic. Furthermore, hardware imple- mentation results typically refer to a single setup and operating point, which is a very limited perspective for a modern communication system, as shown in this thesis.
Several implementations of the single MIMO IDD components, i.e., the detector and the channel decoder, are available for comparison; relevant references are listed in Section 3.3 for the detector and in [34] and [129] for the decoder. Based on the single components, a few attempts were made to provide initial estimations for a complete IDD receiver (e.g., in [88], [148], [169] and [123]).
In view of these issues, the next sections compare the spectral efficiency of the IteRX implementation with the spectral efficiency that can be ideally achieved by relevant alternative algorithms. Firstly, the benefits of selective IDD with respect to non-iterative detection and decoding are highlighted. Secondly, the IteRX receiver is compared to an MMSE-PIC-based IDD system. The comparisons also list the hard- ware requirements for the IteRX design to outperform the alternative algorithms.
5.6.1
Selective IDD vs. Non-Iterative Detection and Decoding
An important goal of this thesis is to assess the hardware implementation costs of MIMO IDD, particularly in comparison with existing non-iterative schemes. Since a consistent comparison with literature data is not possible due to the aforementioned reasons, in this section the maximum spectral efficiency achievable by a non-iterative receiver composed of a soft-output SD detector and the same LDPC decoder used in the IteRX design is taken as the base reference. This case corresponds to the upper- bound performance of the IteRX system limited to a single IDD iteration.
Table 5.3 summarises the minimum hardware requirements for the IteRX design to match or outperform the non-iterative reference spectral efficiency over the com- plete operating range, for different symbol rate constraints. The area savings with respect to a receiver capable of approaching the ideal IDD spectral efficiency (see Ta- ble 5.1) are very significant, reaching 68 % for a 4×4 setup with a 40 Msym/s symbol rate. Reversing the point of view, these area savings correspond to the area overhead required to move the spectral-efficiency curve from the non-iterative case towards the ideal IDD performance. These numbers confirm that the increase of the implementa- tion costs becomes steeper as the system approaches the channel capacity limit.
5.6.2
SD-Based IDD vs. MMSE-PIC-Based IDD
Sphere decoding is not necessarily an obvious choice when selecting which detection algorithm to implement in a MIMO IDD receiver, due to its rapidly increasing com- plexity at low SNR and to its variable runtime. The main motivation to opt for sphere decoding, as explained in Chapter 2, is its superior communication performance to- gether with its robustness to different channel conditions and error-correcting codes. This observation stems from the algorithmic comparison in Chapter 2, mostly based on classical error-rate curves.
A more comprehensive approach is to look at the spectral-efficiency curves achiev- able by the algorithms, computed according to (5.7) without taking into account the limitations of the hardware implementation. Figure 5.16 shows such curves for a floating-point MMSE-PIC detector combined with an LDPC SPA (blue curve) and an
Bs[Msym/s] 1 2 5 10 20 40 2×2 Nidd 1 1 1 1 1 1 Nsd 1 1 1 2 4 7 3×3 Nidd 1 1 1 1 1 2 Nsd 1 1 2 3 7 7 4×4 Nidd 1 1 1 1 2 3 Nsd 1 2 5 10 10 14
Table 5.3: Requirements for the IteRX architecture to match or outperform its non- iterative counterpart for different symbol rates.
LDPC OMS (red curve) decoder after six IDD iterations; it should be noted that no further noticeable performance gain is observed with Iidd > 6. Interestingly, both
curves are derived from floating-point algorithms without any hardware implemen- tation loss and yet they suffer a significant penalty with respect to the IteRX limit curve, up to 3 dB for 16- and 64-QAM modes. This gap is due to the inferior per- formance of MMSE-PIC with respect to STS SD, especially in combination with high code rates, as observed in Section 2.4.
In many operating points, particularly when the code rate is higher than 2/3, MMSE-PIC-based IDD cannot even outperform a non-iterative SD-based receiver. Only for 4-QAM modes the gap among the different curves tends to close. In [148] it is shown that for an IEEE 802.11n LDPC code with R = 1/2, MMSE-PIC needs three IDD iterations to outperform non-iterative soft-output sphere decoding, in a fixed 4×4 64-QAM setup. The previous observations on Figure 5.16 confirm that the benefits of MMSE-PIC over non-iterative SD are limited to very few operating points whereas the drawbacks are visible on a wider range. It should be noted that this con- clusion does not necessarily apply to other channel codes with a worse non-iterative performance but a higher gain over iterations (e.g., convolutional codes).
Table 5.4 summarises the hardware requirements for the IteRX design to match or outperform over the complete SNR range the ideal spectral efficiency of MMSE-PIC detection in combination with LDPC-OMS decoding (red curve in Figure 5.16) at different symbol rates. These requirements are shown for the sake of completeness. In practice, based on the previous analysis, if the design goal is achieving the spectral efficiency of MMSE-PIC, a more efficient choice is to design a non-iterative system based on soft-output SD.
5 10 15 20 25 30 SNR [dB] 0 5 10 15 20 sp ec tr al ef fi ci en cy [b it / s/ H z] 64 QAM, R = 0.83 64 QAM, R = 0.67 64 QAM, R = 0.75 16 QAM, R = 0.83 16 QAM, R = 0.67 16 QAM, R = 0.50 16 QAM, R = 0.75 4 QAM, R = 0.83 4 QAM, R = 0.67 4 QAM, R = 0.50 4 QAM, R = 0.75 upper bounds
MMSE-PIC/LDPC SPA, Iidd=6
MMSE-PIC/LDPC OMS, Iidd=6
IteRX, Iidd=6
IteRX, Iidd=1
Figure 5.16: Spectral efficiency comparison between the IteRX design and two ideal MMSE-PIC-based IDD receivers for a 4×4 AMC setup; the symbol rate is unconstrained, meaning that each curve represents the spectral efficiency upper bound of the corresponding receiver.
Bs[Msym/s] 1 2 5 10 20 40
4×4 AMC using all available MCSs
Nidd 1 1 1 2 3 6
Nsd 2 4 11 11 14 14
4×4 AMC using only MCSs with ηs≥8 bit/s/Hz
Nidd 1 1 1 1 2 3
Nsd 1 2 5 10 10 14
Table 5.4: Requirements for the IteRX architecture to match or outperform an ideal IDD receiver based on MMSE-PIC detection and LDPC OMS decoding for different symbol rates (4×4 AMC setup optimised for spectral efficiency).
Furthermore, if only high spectral efficiency MCSs with ηs ≥8 bit/s/Hz are con- sidered, the requirements drop significantly, as shown by the lower half of Table 5.4. In fact, in this case the (Nidd, Nsd) setups are the same needed by the IteRX design to outperform a non-iterative SD-based receiver (see Table 5.3). This occurs because in such MCSs the communication performance advantage of the IteRX design over an MMSE-PIC-based receiver is relatively larger than in low spectral efficiency modes and hence there is much room to constrain the computational effort.