The dynamic power consumption data of the LDPC decoder refers to the nominal case of Vdd =1.2 V and maximum clock frequency 299 MHz. The input variables are:
• Sub-block size Z; • Code rate R. Z =27 R 1/2 2/3 3/4 5/6 79.27 77.53 76.70 74.55
Table A.4: LDPC decoder power consumption in mW (Z=27).
Z =54 R
1/2 2/3 3/4 5/6
112.65 108.42 107.22 104.53
Table A.5: LDPC decoder power consumption in mW (Z=54).
Z =81 R
1/2 2/3 3/4 5/6
137.52 134.35 134.87 121.61
Acronyms
3G third generation 4G fourth generation
I/O input/output
AGU address generation unit
AMC adaptive modulation and coding ARQ automatic repeat-request
ASIC application-specific integrated circuit BCJR Bahl, Cocke, Jelinek, Raviv
BICM bit-interleaved coded modulation
BICM-ID bit-interleaved coded modulation with iterative decoding BLER block error rate
CDMA code division multiple access
CMOS complementary metal oxide semiconductor CN check node (in a Tanner graph)
CPU central processing unit CRC cyclic-redundancy check CWER codeword error rate
DIBL drain-induced barrier lowering DRC design-rule check
DSP digital signal processing
DVB-H Digital Video Broadcasting - Handheld
DVB-S2 Digital Video Broadcasting - Satellite - Second Generation DVS dynamic supply voltage scaling
ECC error-correcting code
EDGE Enhanced Data Rates for GSM Evolution EP expectation propagation
ETWS early-termination window size
FCC Federal Communications Commission FEC forward error correction (or correcting)
FER frame error rate
FPGA field-programmable gate array FSD fixed-complexity sphere decoding FSM finite state machine
GALS globally asynchronous locally synchronous GDSII Graphic Database System II
GMSK Gaussian minimum shift keying GPRS General Packet Radio Service GPS Global Positioning System
GSM Global System for Mobile Communications HDL hardware description language
HSDPA High-Speed Downlink Packet Access HSPA+ Evolved High-Speed Packet Access i.i.d. independent and identically distributed IC integrated circuit
IDD iterative detection and decoding
IEEE Institute of Electrical and Electronics Engineers LAN local area network
LDD layered detection and decoding LDPC low-density parity check
LL low leakage
LLR log-likelihood ratio LTE Long Term Evolution LVS layout vs. schematic MAC media access control MAP maximum a posteriori MCMC Markov chain Monte Carlo MCS modulation and coding scheme
MF maximum first
MIMO multiple input multiple output
ML maximum likelihood
MMSE minimum mean square error
MP message passing
MPW multi-project wafer NCU node computation unit
OFDM orthogonal frequency division multiplexing OFDMA orthogonal frequency division multiple access OMS offset min-sum
ONPC one node per cycle PAN personal area network
PC personal computer
PCCC parallel concatenated convolutional code PE processing element
PIC parallel interference cancellation QAM quadrature amplitude modulation
QC quasi cyclic
QoS quality of service
QRD QR decomposition
RF radio frequency
RTL register transfer level
SCCC serial concatenated convolutional code SD sphere decoder (or decoding)
SDR software-defined radio
SE Schnorr-Euchner
SNR signal-to-noise ratio SoC system on a chip SP standard performance SPA sum-product algorithm SRAM static random-access memory STS single tree search
UMTS Universal Mobile Telecommunications System
US United States
VHDL very high speed integrated circuit hardware description language VLSI very large scale integration
VN variable node (in a Tanner graph)
WiMAX Worldwide Interoperability for Microwave Access WLAN wireless local area network
Notation – Signal Processing
d diversity gain
MT number of transmit antennae MR number of receive antennae
O set of all the complex scalar symbols belonging to a given constellation
OMT set of all the complex symbol vectors originating from a given constel- lation
Q number of coded bits per complex modulated scalar symbol Es normalised average energy per complex scalar transmit symbol No power spectral density of the additive white Gaussian noise
b information bitstream, input to the encoder on the transmitter side
c coded bitstream, output by the encoder on the transmitter side
s transmit symbol vector
H MIMO channel matrix
n additive noise vector
y received symbol vector
yi complex received symbol on receive antenna i ˆ
s estimated transmit symbol vector, output by the detector on the receiver side
ˆb estimated information bitstream, output by the decoder on the receiver side
Iidd total number of IDD iterations, defined by the number of detector/ decoder runs
iidd index of the current IDD iteration
λa vector of a priori LLRs
λa,det vector of a priori LLRs input to the detector λa,dec vector of a priori LLRs input to the decoder λp vector of a posteriori LLRs
λp,det vector of a posteriori LLRs computed by the detector λp,dec vector of a posteriori LLRs computed by the decoder λe vector of extrinsic LLRs
λe,det vector of extrinsic LLRs computed by the detector λe,dec vector of extrinsic LLRs computed by the decoder
λpi,b a posteriori LLR for the b-th bit on antenna i λai,b a priori LLR for the b-th bit on antenna i λei,b extrinsic LLR for the b-th bit on antenna i
R MIMO channel matrix after QRD
Ri,j element (i, j)of the MIMO channel matrix after QRD
˜
˜yi complex scalar received symbol after QRD on antenna i si complex modulated scalar symbol on transmit antenna i
s(i) partial transmit symbol vector from antenna i to antenna MT
xi,b binary label for the b-th bit of the complex modulated scalar symbol si
on antenna i
xi bit label for the complex modulated scalar symbol si on antenna i x bit label for the complex modulated transmit symbol vector s
Xi,b(±1) set of symbol vectors with the b-th bit on antenna i set to ±1
sML ML symbol vector output by the detector xMLi,b binary label for the b-th bit on antenna i of sML
xML bit label for the ML symbol vector sML
sMLi,b counter-hypothesis symbol vector for the b-th bit on antenna i of sML
sMAP MAP symbol vector output by the detector xMAPi,b binary label for the b-th bit on antenna i of sMAP
xMAP bit label for the MAP symbol vector sMAP
sMAPi,b counter-hypothesis symbol vector for the b-th bit on antenna i of sMAP
M(Ci) partial channel-based metric for the scalar symbol si on antenna i
MC(s) channel-based metric for symbol vector s
MC
s(i) channel-based metric for partial symbol vector s(i)
MML
C channel-based metric of the ML solution sML
M(Ai) partial a priori-based metric for the scalar symbol si on antenna i
MA(s) a priori-based metric for symbol vector s
MAs(i) a priori-based metric for partial symbol vector s(i)
M(Pi) partial general metric for the scalar symbol si on antenna i
MP(s) general metric for symbol vector s
MP
s(i) general metric for partial symbol vector s(i)
MMAPP general metric of the MAP solution sMAP
s(ik) symbol candidate selected by enumeration on antenna i at step k, i.e., after (k−1) nodes have been examined on antenna i
s(A,ik) symbol candidate selected by MA-based enumeration on antenna i at step k, i.e., after (k−1) nodes have been examined on antenna i
s(C,ik) symbol candidate selected by MC-based enumeration on antenna i at step k, i.e., after (k−1) nodes have been examined on antenna i
r2 sphere radius constraint for the tree search
Λe maximum absolute value allowed for clipped extrinsic LLRs Γ clipping value, normalised from Λe according to definition (4.4)
Γcaesar clipping value, normalised from Λe according to definition (3.4) Nen number of examined nodes in a single detector run
Nen,i number of examined nodes (same as Nen) in the i-th IDD iteration Nen,c number of examined nodes cumulated over multiple detector runs, i.e.,
over multiple IDD iterations
Nen,max maximum number of examined nodes allowed in a single detector run Nen,max(i) maximum number of examined nodes allowed on antenna i
ˆ
Λe correction vector for clipped extrinsic LLRs
ˆ Λe
i k-th entry of the correction vector ˆΛ
e ˆλe
i,b corrected extrinsic LLR for the b-th bit on antenna i
Λp LLR threshold for symbol-wise on-demand detection
Λe magnitude of the new LLR for symbol-wise on-demand detection iy˜ index of a given symbol vector within all the vectors in a codeword
Ny˜ number of symbol vectors in a codeword C codebook of an error-correcting code Ni number of information bits in a codeword
Nc number of coded bits in a codeword (i.e., codeword length)
R code rate
Gb LDPC code generator matrix
Hb LDPC code parity-check matrix
Z sub-block size of IEEE 802.11n LDPC codes
Mp number of rows of an IEEE 802.11n LDPC matrix prototype Np number of columns of an IEEE 802.11n LDPC matrix prototype
Hp IEEE 802.11n LDPC matrix prototype
Pc cyclic-shift matrix
ck k-th coded bit in the codeword
λpk a posteriori LLR for the k-th bit in the codeword qv,c Message from variable node v to check node c
rc,v Message from check node c to variable node v
Nvn(c) set of neighbouring variable nodes to check node c Ncn(v) set of neighbouring check nodes to variable node v
β offset for correcting the messages rc,v in the OMS decoding algorithm
Idec number of LDPC iterations
B bandwidth in Hz
Bs symbol rate in sym/s
Bs,min minimum symbol rate requirement in sym/s Bs,max maximum symbol rate constraint in sym/s
Θ
i ideal information (or coded) throughput achievable in the absence of errors, in bit/s
Θi,min minimum ideal information (or coded) throughput achieved at symbol rate Bs,min, in bit/s
Θi,max maximum ideal information (or coded) throughput achieved at symbol rate Bs,max, in bit/s
ηs spectral efficiency in bit/s/Hz
Nf total number of decoded codewords (or frames)
Notation – Integrated Circuits
nemu number of parallel instances of a certain component implemented in a given FPGA-based emulator
MT,max maximum number of transmit antennae supported by a given architec- ture
Qmax maximum number of coded bits per complex modulated scalar symbol supported by a given architecture
CC cycle count for a given task fclk operating clock frequency in Hz fmax maximum clock frequency in Hz Vdd operating supply voltage in V Vdd,n nominal supply voltage in V Vth threshold voltage in V Is average static current in A Ps average static power in W Pd average dynamic power in W
S feature size ratio between two silicon technologies
U nominal supply voltage ratio between two silicon technologies Acore area occupied by one SD core in the Caesar chip in GE
Achip core area occupied by the Caesar chip in GE
Ps,core average static power consumed by one SD core in the Caesar chip in W Ps,chip average static power consumed by the Caesar chip in W
Θcaesar information (or coded) throughput of the Caesar architecture in bit/s
Gcaesar goodput of the Caesar architecture in bit/s Acaesar area occupied by the Caesar architecture in GE ηa,caesar area efficiency of the Caesar architecture in bit/s/GE
Pcaesar average total power consumed by the Caesar architecture in W ηe,caesar energy efficiency of the Caesar architecture in bit/J
CCdetc cycle count for detecting a complete codeword (cumulated over IDD iterations)
CCdetc, ideal ideal cycle count for detecting a complete codeword on a multicore detector (cumulated over IDD iterations)
CCdetmax maximum cycle count allowed for detecting a complete codeword (sin- gle IDD iteration)
CCdecit cycle count for one internal decoding iteration
CCdec cycle count for decoding a complete codeword (single IDD iteration) Aidd area of the IDD receiver in GE
fmax,det maximum clock frequency of the MIMO detector in Hz fmax,dec maximum clock frequency of the LDPC decoder in Hz
Θpe information (or coded) throughput of a processing element in bit/s Θ
det information (or coded) throughput of the MIMO detector in bit/s Θdec information (or coded) throughput of the LDPC decoder in bit/s Θidd information (or coded) throughput supported by the IDD receiver hard-
ware implementation in bit/s
Θidd,c information (or coded) throughput constrained by hardware imple- mentation and bandwidth requirements, in bit/s
Giterx goodput of the IteRX architecture in bit/s
Gc goodput constrained by hardware implementation and bandwidth re- quirements in bit/s
ηs,c spectral efficiency constrained by hardware implementation and band- width requirements in bit/s/Hz
ηa,idd area efficiency of the receiver in bit/s/GE Ps,idd static power consumed by the receiver in W Pd,det dynamic power consumed by the detector in W Pd,dec dynamic power consumed by the decoder in W ρpe utilisation ratio of a processing element
ρdet utilisation ratio of the MIMO detector ρdec utilisation ratio of the LDPC decoder
Es,idd static energy consumed by the IDD receiver while processing Nf code- words, in J
Ed,det dynamic energy consumed by the detector for processing Nf code- words, in J
Ed,dec dynamic energy consumed by the decoder for processing Nf code- words, in J
Eidd total energy consumed by the IDD receiver for processing Nf code- words, in J
Tdet total detector execution time for processing Nf codewords, in s Tdec total decoder execution time for processing Nf codewords, in s