The analysis presented in this chapter aimed at proving the importance of a com- prehensive view on the evaluation of single components or subsystems of a wireless communication system. To this end, the definition of the proper relevant metrics and of realistic scenarios applicable to modern systems is key. In the first part of the chap- ter, efficiency metrics were specified to enable the evaluation of various aspects of the component behaviour in a system context, taking into account the capabilities and limitations of both the algorithm and its silicon implementation. The main considera- tions relate to the data rate, to the efficient use of the available bandwidth and to the energy consumption.
The communication setup and the receiver settings can be adapted to optimise any of these targets, exploiting the capabilities of the system to switch among differ- ent modulation schemes, code rates and, possibly, symbol rates. If a high spectral ef- ficiency is the priority, large constellations and high code rates are used as extensively as possible. On the other hand, energy can be saved in the receiver by using modes with a lower number of bits per channel use. Similarly, for a variable-complexity receiver, high data rates (i.e., goodputs) are achieved more easily by combining low- order modulations with high symbol rates than by using higher spectral efficiency modes, with more bits per channel use, and a lower symbol rate.
Aside from these general remarks, throughout the chapter it has been shown how the usage of iterative detection and decoding can improve the performance of the system, particularly in terms of spectral efficiency, even taking into account the lim- itations of the hardware implementation. The costs of this advanced technique were analysed, showing that from a system perspective the energy and latency overhead is relatively small. Subsequently, the hardware requirements to support MIMO IDD for different numbers of spatially-multiplexed streams and symbol rates were derived. This analysis showed that IDD can be already beneficially applied to a high data rate MIMO system, especially when factoring in the potential of techniques that are nowadays standard in commercial silicon implementations, such as supply voltage scaling.
Conclusions and Outlook
Spatial-multiplexing MIMO has been adopted in recent wireless communication stan- dards to boost the data rate and to effectively exploit the limited resources available in today’s crowded frequency spectrum. Applying iterative detection and decoding to a MIMO system enables the further enhancement of the spectral efficiency. This signal processing approach has been studied extensively on an algorithmic level and, more recently, also in the perspective of hardware implementation.
This thesis described the process of implementing a MIMO IDD receiver in sil- icon, from the initial algorithmic analysis to the characterisation of the fabricated prototype, which is the first one of its kind reported in the literature, to the best of the author’s knowledge. In this final chapter, the main steps and contributions are first summarised and then a few concluding remarks based on the implementation results are given. Finally, a number of suggestions for possible future research directions are listed, that build upon the ideas presented in this thesis.
6.1
Summary
The implementation of any wireless receiver component always follows a preliminary analysis of the available options from an algorithmic standpoint. MIMO IDD pro- cessing consists of the interaction of two components, i.e., the MIMO detector and the channel decoder. Accordingly, in Chapter 2 the most prominent soft-input soft-output algorithms suitable to realise the two functionalities were surveyed and compared in terms of communication performance. A key point of such an analysis is that it can- not be limited to a single isolated component and operating scenario, which gives an incomplete perspective. Therefore, in order to avoid misguided design decisions, several detector/decoder combinations were tested under different conditions.
Although the algorithmic analysis is very valuable, hardware-related considera- tions must be included in the process of selecting the algorithms for the implementa- tion. To this end, Chapter 3 described the first silicon implementation of a soft-input soft-output depth-first sphere decoder. While this max-log MAP optimal algorithm provides the best all-round communication performance for MIMO detection, its sil- icon feasibility and area/energy implementation costs had not been previously as- sessed by post-fabrication measurements. The complexity of SD can be tuned to the channel conditions and to the target error rate, which enables its hardware imple- mentation to achieve the max-log MAP optimal performance while reaching very competitive efficiency figures at high SNR.
This ability to trade off efficiency vs. performance is a distinguishing trait of sphere decoding, making it the algorithm of choice for the MIMO detection func- tionality in the MIMO IDD receiver prototype presented in Chapter 4. On the other hand, channel decoding was realised by an IEEE 802.11n-compliant LDPC decoder, characterised by good error-correcting capabilities and at the same time well-suited for a high-throughput multi-mode hardware implementation. Similarly to sphere de- coding, LDPC decoding can span the efficiency vs. performance tradeoff by varying the number of its inner iterations. After finalising the choice of the two algorithms, several heuristic techniques were introduced in Chapter 4 to reduce the complexity of the MIMO IDD receiver, without compromising its communication performance.
After optimising the system on the algorithmic level, a MIMO IDD architecture was introduced based on a ping-pong interleaved schedule between the detector and the decoder, which maximises the throughput. While the basic sphere decoding and LDPC decoding components mostly built upon formerly existing architectures, the challenges of assembling them into an efficient system were tackled in Chapter 4.
First of all, multiple SD instances were put together to form a high-throughput detector. In order to approach the ideal speedup achievable by parallelisation, the I/O logic was designed to load and store one received symbol vector per cycle. Fur- thermore, several scheduling policies were analysed to enable the detector to meet real-time deadlines with a minimum impact on the communication performance. The resulting architecture is highly scalable and was proven on gate level not to suffer from any penalty in terms of maximum clock frequency for up to 64 SD instances.
The second main challenge in the MIMO IDD receiver implementation is the design of a shared LLR memory accessible by both processing elements without throughput penalties. This goal was achieved by a custom standard cell-based mem- ory architecture capable of serving the high bandwidth required by the LDPC de- coder. In conjunction with a specialised address generation and alignment unit, this architecture can also deal with the varying access patterns of the MIMO detector. The implementation issue of interfacing the memory with different clock domains at dif- ferent times was solved by switching its clock to that of the connected PE, rather than introducing extra latencies by synchronising the data signals at the interface.
The receiver architecture was implemented in a 65 nm low-power CMOS technol- ogy with five SD instances. The prototype can achieve throughput figures well above 1 Gbit/s and is capable of approaching the max-log MAP performance at low SNR, by trading off efficiency vs. performance. An extensive exploration of this tradeoff was presented in Chapter 5. The analysis takes into account the communication system constraints, such as the symbol rate, and how they relate to the hardware implemen- tation metrics. The many parameters that can be configured in the receiver and in the communication system were optimised with respect to different targets, such as the spectral efficiency, the goodput and the energy efficiency of the system. The results show that significant gains can be achieved in the specific metric targeted by the opti- misation. Furthermore, the benefits of MIMO IDD were shown in Chapter 5 and the costs for deploying it in a modern communication system were quantified based on the measurements performed on the silicon prototype.