Continuous Approaches

Geometric Program Based

The mathematically best founded approaches rely on the geometric program formu- lation. A posynomial-based formulation was first presented by Fishburn and Dunlop [FD85] for the transistor sizing problem with the Elmore delay model [Elm48] for transistor delays. Sapatnekar et al. [Sap+93] were the first to compute exact so- lutions for the transistor sizing problem with a general-purpose solver for convex programs under a variant of the Elmore delay model. Kasamsetty et al. [KKS00] proposed a more accurate posynomial delay model for gate delays than the El- more delay model, and applied the same optimization approach as Sapatnekar et

al. [Sap+93]. General-purpose solvers for geometric programs usually implement interior point methods with polynomial running time. Unfortunately, interior point methods consume significant memory and running time which makes them unsuit- able for large instance sizes as they occur in gate sizing. The largest instance sizes reported to be solved (Joshi and Boyd [JB08]) come from gate sizing and contain up to 100000 gates. The authors reported that for larger instance sizes their cus- tomized geometric program solver, which implements a primal-dual interior point method, failed to provide a solution. Additionally, running times were expensive (“tens of hours”). The authors further developed a truncated Pseudo-Newton ap- proach that allowed them to tackle larger instance sizes of up to one million gates. Unfortunately, they could not give any theoretical bounds on the quality of their solution, and they could only establish optimality of their solutions for the smaller instances by comparison with a customized geometric program solver.

Additionally, the geometric program for gate sizing was tackled by several re- searchers using standard solvers as well as custom methods under different posyn- omial delay models. For example, Menezes et al. [MBP97] applied sequential quadratic programming and approximated the objective function by a quadratic function, and the constraints by linear functions.

Boyd et al. [Boy+05] provide a tutorial on the geometric program formulation and show how more constraints and objectives such as supply voltage and Vt level

optimization can be included in the geometric program.

Lagrangian Relaxation

Marple [Mar89] proposed to relax the timing constraints of the transistor sizing problem with Lagrange multipliers. He applied the Lagrangian augmentation tech- nique, where an extra penalty term is added to the Lagrange function to steer the solution towards the feasible region.

Chen et al. [CCW99] give a thorough introduction into Lagrange relaxation for the gate sizing problem. They show that the Lagrange function can easily be simplified when the Lagrange multipliers are restricted to the non-negative network flow space, in other words they fulfill the flow conservation rule at all vertices v ∈ V \ {Vstart∪ Vend}. This is not possible with the Lagrangian augmentation

technique. The projected subgradient method solves the dual problem, and in each iteration a greedy algorithm for the Lagrange primal problem computes a new subgradient. The Lagrange multiplier projection to the non-negative flow space can be formulated as quadratic cost flow problem and is solvable in polynomial time. Chen et al. [CCW99] observed that exact projection dominated the running time of their algorithm and used a heuristic projection step instead. Further constraints, for example on clock skew, can easily be incorporated into the geometric program and be relaxed by Lagrange multipliers. The approach can be extended to more accurate posynomial delay models, see for example Rahman et al. [RTS11]. The fact that the duality gap is zero if a strongly feasible solution for the geometric program exists further encourages its use. The work of Chen et al. [CCW99] is the

4.7 Previous Work

groundwork for Lagrange relaxation based algorithms for both the continuous and the discrete problem. Wang et al. [WDZ07] provide further theoretical analysis on this formulation, and show that the dual objective function is differentiable, allowing the use of the projected gradient method. The Lagrange relaxation approach, related subproblems and extensions will be discussed in detail in Chapter 6 and Chapter 7.

Linear Programming and Network Flows

The simplest model of the continuous relaxation linearizes the delays and the objec- tive function (Berkelaar and Jess [BJ90], Chinnery and Keutzer [CK05]). Nguyen et al. [Ngu+03] use a linear program to distribute slacks to the gates in the design, and realize these targets with gate sizing and Vt assignment. Vygen [Vyg01] and

Ren and Dutt [RD08; RD13] model gate sizing as slightly different minimum-cost network flow problems. Available sizes and their costs are encoded in a graph, and the flow indicates which sizes are used in an optimal solution.

Continuous-guided

Continuous-guided approaches compute an optimal continuous solution and use it as a basis for further optimization. However, rounding a continuous solution is not an easy task and the literature on rounding is sparse. It was observed in practice that choosing the “closest” discrete solution can lead to large timing violations, see for example Hu et al. [HKH09] and Rahman et al. [RTS11]. To overcome this problem, Hu et al. [HKH09] propose to evaluate several discrete sizes close to the continuous solution with dynamic programming. The gates are traversed via breadth-first search, and several sizing solutions are propagated for each gate. Solutions are pruned based on path delays and area consumption. In the branch-and-bound approach of Rahman et al. [RTS11], the solution set for each gate consists of a set of sizes close to the continuous solution. Chuang et al. [CSH95] take a linear program solution and allow the next smaller and next larger size as option for each gate. Gates already set to their minimum size are not changed, but for the remaining gates all allowed options are enumerated. This yields near-optimal results, indicating that the sizes in an optimal discrete solution are not necessarily the closest to the continuous solution. Wu and Davoodi [WD08] employ a branch-and-bound algorithm to compute optimal discrete gate sizes, and consider solutions obtained by different rounding strategies for comparison. They conclude that rounding to the closest discrete solution yields large timing violations, which are then fixed by iteratively increasing gate sizes. This comes with an objective function increase by up to 51%. A branch-and-bound technique with a restricted feasible set that consists of the next smaller and the next larger gate size returned solutions with objective function values that are only 0.7% larger than in the optimal solution in average. A recent paper of Xie and Chen [XC15] presents a modified Elmore delay model for the ISPD 2012 benchmarks. A continuous solution is computed with

a Lagrangian relaxation based algorithm, and nearest rounding combined with a postoptimization step returns a discrete solution. Shah et al. [Sha+05] propose a novel formulation for continuous sizing and Vt optimization that models different

Vt levels for a gate as a single circuit which is a parallel combination of the high

and low Vt gate. Without constraints on the gate sizes, the Vt levels are all set to

a feasible discrete value in an optimal solution.

Farshidi et al. [Far+13] regard gate sizing as a multi-objective optimization prob- lem with objectives power, area and delay minimization. The objective of their geometric program formulation is the weighted sum of conflicting objectives for gate sizing, and the weights are also regarded as variables.