Interior Point Methods

A new iterate x(k+1) is computed as a convex combination of the previous iterate x(k) and a feasible descent direction. The factor of the descent direction in the convex combination decreases in each iteration. The feasible direction is computed by solving a minimization problem of the form

min ∇f x(k)
t

x − x(k)
< 0 subject to x ∈ X.

In order to find a finite solution to the minimization problem, X has to be compact.

3.4 Interior Point Methods

We consider interior point (IP) methods for convex problems of the form (3.1) with inequality constraints only (i.e. l = 0) and X = Rn. Interior point methods solve linear and convex optimization problems in polynomial time. The first polynomial time interior point method was developed by Karmarkar [Kar84] for linear pro- gramming, and later generalized for convex programming. Many different variants of this method exist, which all have in common that they traverse the interior of the feasible region to find an optimal solution. For nonlinear programming, primal-dual methods are increasingly popular (Forsgren et al. [FGW02]), and outperform the barrier method on several problem classes including geometric programming (Boyd and Vandenberghe [BV04]). We give a short description of the basic functionality. The interior of the set which is defined by the inequality constraints is incorporated into the objective function by means of a barrier function: This continuous function is only defined on the interior of this set, and approaches infinity as any of the inequality constraints approaches 0 from negative values. b(x) = −Pm

i=1ln(−gi(x))

is an example of such a barrier function.

Starting at a strongly feasible solution x, the barrier method iteratively solves minx∈X(f (x) − Pm_i=1(1/t) ln(−gi(x))), which approximates problem (3.1), with

Newton’s method for increasing t. It returns the solution from the last iteration. Starting with a strongly feasible solution, primal-dual interior point methods itera- tively step in a so-called primal-dual search direction with a certain step size. The search directions are computed by solving a system of modified KKT-conditions with Newton’s method, and are closely related to the search directions used in the barrier method. In contrast to barrier methods, primal and dual variables, which are defined as λi:= −1/(t · gi(x)), are updated in each iteration.

Rather informally, the worst-case complexity is approximately proportional to the number of Newton steps. The idea behind Newton’s method is to approximate the objective function by a quadratic function, and then take a Newton step towards the minimum or a saddle point of the quadratic function. The Newton step is defined as the negative of the gradient multiplied with the inverse of the Hessian matrix. It is necessary to compute the first and second derivative of the barrier function, and solving the Newton system has complexity O(n3) in general (Nemirovski [Nem04]).

4 Gate Sizing and Vt

Optimization

A key challenge in the physical design of a computer chip is to choose a layout for each gate. Thereby the most common objectives are to minimize the power consumption or area of the chip subject to constraints on the speed of the electrical signals. The most influential characteristics of a gate are its size and Vt level, and

we refer to the problem of choosing a layout as gate sizing and Vt optimization

problem. With the continuing technology scaling and growing transistor count, gate sizing and Vt optimization have become increasingly important (cf. Section

2.1). Additionally, both characteristics have large impact on signal delays and electrical integrity, and a good choice is essential to achieve timing closure. Often, gate sizing and Vtoptimization are treated separately.

Optimization is deployed at several stages during the physical design flow. Be- sides the versatility of the objective function, both operations are less disruptive than changing the placement of circuits or rerouting nets to fix timing constraint violations, especially in later design stages. The most common application area is in the timing optimization step. At this point, registers, in particular their sizes, have usually been fixed along with the clock net routing, and changing them would require rerouting the clock net. Therefore most algorithms consider only logic gates for optimization. Often gate sizing is performed incrementally and in combination with other algorithms for timing optimization, for example repeater insertion and timing-driven detailed placement.

The application range for sizing and Vt optimization further contains post-routing

optimization, where only small changes should be made, and gate sizing that takes place after an initial placement, but before the clocks are fixed. Simplified delay models are used in that early stage.

Having analyzed the power consumption of a gate in Section 2.1, we discuss the dependency of signal delay on gate layouts in Section 4.1. We continue with a formal definition of the gate sizing problem, its continuous relaxation and the geometric program formulation (Section 4.2 - 4.4). In the continuous relaxation, gate sizes are restricted to intervals. The Vt optimization problem is introduced in Section

4.5. Afterwards, we review existing literature on the computational complexity of these problems (Section 4.6) and previous work (Section 4.7). Common approaches can be divided into continuous and discrete approaches. Continuous approaches target the continuous relaxation of the gate sizing problem, which is solvable in polynomial time and both of practical and academic interest. Several algorithms round a continuous solution to a discrete solution. We address the complexity of rounding in Section 4.8, and draw comparisons between discrete and continuous approaches in Section 4.9.

4.1 Delay Characteristics of Gate Sizes and V

levels

Gate Sizes

The most influential characteristic of a gate is its size. Modern libraries usually contain between ten and twenty different sizes for each elementary logic function which differ in their transistor widths. The number of sizes for registers is usually smaller. Figure 4.1 shows simplified layouts for an inverter gate. Each layout real- izes a different size by varying the transistor widths. For larger sizes, the transistors must be folded which in turn increases the width of the inverter gate. Gates belong to the class of so-called standard circuits which have in common that they need to fit in the cell rows between the Vdd and V0 rails, and only vary in their widths. For

details on transistor layout of circuits we refer to Schneider [Sch14].

Input Output Vdd

V0

p-type transistor

n-type transistor _Width Width

. .

Figure 4.1: Different layouts for an inverter gate realizing different sizes as seen from above. In the layout on the right the transistors have been folded to fit into the gate. Note that the ratio between the sizes of n-type and p-type transistors usually varies.

A larger size has higher drive strength and allows faster charging and discharging of load capacitances. It accelerates a voltage change at the output pin of a circuit, and decreases the outgoing slew. On the downside, a larger size requires more area on the chip and consumes more total power than a smaller size due to larger input pin capacitances. Consequently, delay and slew of signals entering the input pin, which are also propagated to sibling circuits, deteriorate.

Vt Level

The threshold voltage, or Vt level, defines the voltage at which a gate switches.

4.1 Delay Characteristics of Gate Sizes and Vt levels

The highest Vt level corresponds to the highest threshold. Lowering the Vt level

of a gate accelerates signals, as the gate can switch earlier and thereby propagate signals faster. The impact of Vtlevel changes on input pin capacitances, and hence

the impact on delay of input signals, is relatively small and usually neglected.

Beta Ratio and Tapering

Two more important characteristics of a gate that influence signals delays are its

beta ratio and tapering. The beta ratio of a gate is the ratio of the sizes of its n- Beta ratio

type and p-type transistors. Changing the ratio either accelerates the rising or the

falling signal. Tapering can be applied to gates with more than one input pin that Tapering

contain serially arranged transistors. Thereby the relative sizes of serially arranged transistors are modified with the aim to improve the delay of certain propagation segments in the gate. In this thesis we focus on optimizing sizes and Vt level.

Common Concepts

Both gate sizing and Vt optimization contain the task to choose layouts that re-

alize a good tradeoff between power consumption or area, and signal speed. Vt

optimization is easier than gate sizing in the sense that increasing the power or area consumption more predictably leads to a delay decrease and vice versa, as the impact on input pin capacitances is relatively small. The same is not always true for gate sizing, because larger sizes can slow down predecessor and sibling gates and increase the sum of delays. This can be disadvantageous, as the sum of delays on each path in the timing graph needs to be small enough in order to fulfill the timing constraints.

Gate sizing and Vt optimization are two separate optimization problems in VLSI

design, but there is a tendency to handle them simultaneously. In this thesis we focus on theory and algorithms for gate sizing that can easily be extended to incor- porate Vt optimization, for example the Lagrange relaxation approach. Heuristic

subroutines that evaluate the impact of changing a gate layout on signal delays locally are often used in these algorithms. As changing the Vt level causes less dis-

ruption locally than changing the size, it is often easy to extend sizing algorithms to incorporate Vtoptimization.

This could also lead to the assumption that changing the Vt level of a gate is

preferable to changing its size. On the contrary, the exponential dependency of static power consumption on the Vt level makes changing the size more preferable

in many situations. Having said that, lowering the Vt level can be preferable to

increasing the gate size, for example if a signal needs to be accelerated, but a larger size would introduce a load or slew violation at its predecessors or would slow down the input signal. Handling gate sizing and Vt optimization simultaneously has the