The Control of the Data Flow Between a FPGA and the DSP

The access to the data bus and the data flow is controlled by the DSP. It has absolute control over the main address bus. The DSP is the master of the data bus and all the other devices accessing it are slaves. In the FPGAs, the two main modules involved in the process of interfacing the

CHAPTER 4 — FIRMWARE DESIGN FOR THE PROGRAMMABLE LOGIC DEVICES 38

FPGAs to the data bus are Addr Dec Ctrl and Data Ctrl. The Addr Dec Ctrl module decodes the address on the main address bus of the system and generates an enable signal for the register addressed. The Data Ctrl module uses these enable signals to direct the data from its source to its destination. Data can either be send from the main data bus to a register or from a register to the main data bus.

The Data Bus Multiplexor

In this section it is explained how the main module responsible for interfacing the FPGA to the data bus, operates. Figure 4.1 is a diagram of the module.

Input Register 0 CLK RESET Data_Ctrl Input Register 1 Input Register m

Input Register 0 Enable Input Register 1 Enable

Input Register m Enable

DATA 16 RnW Output Data 0 Output Data 1 Output Data n

Output Data 0 Enable Output Data 1 Enable

Output Data n Enable

...

...

...

...

Figure 4.1: Diagram of the Data Ctrl Module

The module implements registers to store data received from the main data bus. The data in these registers is available to the rest of the FPGA through the input register outputs as shown in the diagram. Each of the registers implemented in other modules of the system responsible for transfering data to the data bus, has an output data input to the Data Ctrl module. An input register typically contains the configuration data for one of the devices like an ADC, while an output data input is connected to a register containing data like the data sampled by one of the ADCs which have to be transferred to the DSP via the data bus. Both the transfer of data from the data bus to the input registers and the transfer of data from the output data inputs to the data bus, are controlled by the enable signals generated by the Addr Ctrl module. The operation of this module is explained in the section ”The Address Decoder”.

CHAPTER 4 — FIRMWARE DESIGN FOR THE PROGRAMMABLE LOGIC DEVICES 39

Figure 4.2 is a simplified diagram showing the interconnection of the modules used to imple- ment the Data Ctrl module, emphasizing the data flow paths.

Input Register 0 CLK RESET Data_Ctrl Input Register 1 Input Register m Input Register 0 Enable

Input Register 1 Enable

Input Register m Enable

DATA

Output Data 0 Output Data 1

Output Data n

Output Data 0 Enable Output Data 1 Enable

Output Data n Enable

... ... OUT_DATA Bidir BIDIR IN_DATA IN_DATA SEL MyBuf OUT_DATA IN_DATA SEL MyBuf OUT_DATA IN_DATA SEL MyBuf OUT_DATA ... ... Combinatorial Multiplexing Logic

Figure 4.2: Detailed Diagram of the Data Flow Through the Data Ctrl Module

To interface with the bi-directional data bus of the system, the Data Ctrl module contains a

Bidir module which is shown in Figure 4.3. Its BIDIR port is connected to the DATA port of

IN_DATA RnW CLK Bidir 16 BIDIR 16 OUT_DATA 16

Figure 4.3: Diagram of the Bidir Module

Data Ctrl. When data is transferred from the data bus to the FPGA, the RnW input of the Bidir

module is driven HIGH, which causes the module to put its BIDIR ports in the high-Z state, making it possible to read data placed on the data bus. The module outputs the data read on the

CHAPTER 4 — FIRMWARE DESIGN FOR THE PROGRAMMABLE LOGIC DEVICES 40

to the correct destination module. The MyBuf module, shown in Figure 4.4 is a register. Its operation is very simple. Whenever the SEL input is HIGH, the module’s data input (IN DATA) is copied to its data output (OUT DATA) or else the data output stays the same. The SEL inputs are provided by the enable signals originally created in the Addr Dec Ctrl module. The

IN DATA inputs of all the MyBuf registers were connected to the OUT DATA port of the Bidir

module. The OUT DATA outputs of the MyBuf module then provide the data to the rest of the system. When data have to be transferred to the data bus, it is placed on the IN DATA input of

IN_DATA SEL RESET MyBuf n n OUT_DATA Parameters: n: interger 0 to 15

Figure 4.4: Diagram of the MyBuf Module

the Bidir module. This proved to be a bit more complicated to implement, because the outputs of more than one register have to be multiplexed to one data input. A modified MyBuf module was created. Its output was like the previous version equal to its input when the SEL signal was HIGH, but placed in the high-Z state when the SEL input is LOW. Although none of the enables connected to the SEL inputs of the modified MyBuf modules (which is generated by the Addr Dec Ctrl module) are ever active at the same time, the Max+Plus II compiler did not allow this configuration stating that the IN DATA input has multiple sources. The problem was solved by multiplexing each bit of the IN DATA input individually.

The Address Decoder

In this section the operation of the Addr Dec Ctrl module is discussed. This module is respon- sible for the generation of the register enable signals that are sent to the Data Ctrl module. Figure 4.5 and Figure 4.6 are diagrams showing the interfaces of Addr Dec Ctrl module for the two FPGAs. The only difference is the inclusion of a strobe input, nSTRB, which is received from the DSP in the Addr Dec Ctrl module implemented in FPGA Main. As can be seen in the diagram, there are two types of enable signals, input register and output data enable signals as explained in the previous section. The ADDR input is the 10 least significant bits of the system’s main address bus. For FPGA Analog, the FPGA nCS input is received from FPGA Main and is the combination of the active LOW chip select signal () for FPGA Analog and

the active LOW data bus strobe signal ( ) generated by the DSP using a logical OR op-

eration. Therefore, only if both the chip select for FPGA Analog and the data bus strobe are active (LOW), the chip select for the ADDR Dec Ctrl will be active. For FPGA Main the

CHAPTER 4 — FIRMWARE DESIGN FOR THE PROGRAMMABLE LOGIC DEVICES 41

and input signals were kept seperate and only combined inside the module. The RESET

input is used to reset the module and the CLK input is the clock signal regulating the module.

CLK RESET

Addr_Dec_Ctrl

Input Register 0 Enable Input Register 1 Enable

Input Register m Enable

FPGA_nCS

Output Register 0 Enable Output Register 1 Enable

Output Register n Enable

...

...

ADDR

10

nSTRB

Figure 4.5: Diagram of the Addr Dec Ctrl Module of FPGA Main

CLK RESET

Addr_Dec_Ctrl

Input Register 0 Enable Input Register 1 Enable

Input Register m Enable

FPGA_nCS

Output Register 0 Enable Output Register 1 Enable

Output Register n Enable

...

...

ADDR

10

Figure 4.6: Diagram of the Addr Dec Ctrl Module of FPGA Analog

The core of the Addr Dec Ctrl module is the Addr Element module. In actual fact the whole

Addr Dec Ctrl module is just a collection of these modules, one for each register which needs

an enable signal. Figure 4.7 and Figure 4.8 are the diagrams of this module for FPGA Main and FPGA Analog respectively. Each of these modules has a unique address input constant (INT ADDR) which corresponds to the address of the register represented by the particular

Addr Element module. This address is compared to the input address (ADDR) on every LOW to

HIGH transition of the input clock signal (CLK). For FPGA Main the enable output (EN) will be activated only if the input address corresponds with the address constant and the logical OR of the chip select signal (nCS), and the data strobe signal (nSTRB) is LOW. For FPGA Analog the enable output will be activated only if the input address corresponds with the address constant and the chip select signal (nCS) is LOW.

CHAPTER 4 — FIRMWARE DESIGN FOR THE PROGRAMMABLE LOGIC DEVICES 42 Parameters: INT_ADDR: interger 0 to 1023 CLK RESET Addr_Element EN nCS ADDR 10 nSTRB

Figure 4.7: Diagram of the Addr Element Module of FPGA Main Parameters: INT_ADDR: interger 0 to 1023 CLK RESET Addr_Element EN nCS ADDR 10

Figure 4.8: Diagram of the Addr Element Module of FPGA Analog