In this section the firmware design for the EPLDs is discussed. The main function of the EPLDs is to provide the interface between the DSP and the two expansion busses. Each of the EPLDs controls one of the expansion busses. The physical layout of the two EPLD expansion bus systems was done exactly the same. This implies that the same firmware design can be loaded on both the EPLDs without the need to make changes to pin assignments before loading the firmware to the two EPLDs.
4.4.1
The Complete Expansion Bus Module
The module implemented in the EPLDs is the EXBUS Single Complete module. This module is shown in Figure 4.41. Its interface with the expansion bus consists of the following. It has
EXBUS RDYnBSY DATA A_nEN D_nEN nACK CLK nRESET ExBus_Single_Complete n n ADDR n nINT nINTREQ_OUT nCS RnW nINTREQ_IN DSP_RnW DSP_nSTRB
Figure 4.41: Diagram of the ExBus Single Complete Module
a bidirection bus, EXBUS, for the transfer of data and addresses. The interface has five control lines. The A nEN and D nEN outputs signal whether the data on the expansion bus is an address or the data that has to be transferred. The RnW output indicates whether it is a read or a write transaction that is being processed. The external device connected to the expansion bus signals the module with the nACK input when it had processed the data on the bus. It can also send an interrupt request with the nINTREQ IN to the module.
The module’s interface with the DSP consists of the following. It has a bidirectional bus, DATA, that connects directly to the system data bus. There is also a 16-bit input, ADDR, which is connected to the system address bus. The DSP RnW and DSP nSTRB inputs are the DSP’s transaction type (read or write) and data bus strobe signals.
The module receives a chip select signal from FPGA Main through the nCS input. This input is activated when the address on the address bus is in the range assigned to the specific expansion
CHAPTER 4 — FIRMWARE DESIGN FOR THE PROGRAMMABLE LOGIC DEVICES 78
bus. The module sends three control signals back to FPGA Main. The RDYnBSY output indi- cates whether the module is ready for a new transaction or is still busy processing a previous one. The nINT output is pulsed when the expansion port receives data from the external device connected to it. This signal can then be used by FPGA Main to trigger the DSP to read the new data from the expansion port module. The module outputs the interrupt received from the
nINTREQ IN input, to FPGA Main through the nINTREQ OUT output. The module receives
its global clock signal of 30MHz from FPGA Main through the CLK input. FPGA Main can reset the module through the nRESET input. Figure 4.42 is a diagram of the modules used to construct the ExBus Single Complete module. It can be seen in the diagram that the module is
EXBUS_IN RDYnBSY DATA_OUT A_nEN D_nEN nACK CLK RESET ExBus_Ctrl n n ADDR n nINT nCS EXBUS_RnW DSP_RnW DSP_nSTRB EXBUS_OUT n RnW n DATA_IN IN_DATA RnW CLK Bidir n n BIDIR OUT_DATA n DSP_RnW DATA IN_DATA RnW Bidir n BIDIR n OUT_DATA n CLK A_nEN D_nEN nACK RnW ADDR nRESET CLK RDYnBSY nINT EXBUS nCS nINTREQ_IN nINTREQ_OUT DSP_nSTRB ExBus_Single_Complete
Figure 4.42: Diagram of the Components of the ExBus Single Complete Module
constructed using only two types of modules. The Bidir module is the same as the ones used in FPGA Main and FPGA Analog. It is used to handle the transfer of data to and from the two bidirectional busses, DATA and EXBUS. For a more detailled explanation refer to section 4.1.1. The other module, ExBus Ctrl, is used to implement the data transfer protocol of the expansion bus.
4.4.2
The Expansion Bus Control Module
The module implementing the data transfer protocol of the expansion busses, is the ExBus Ctrl module. Figure 4.43 is a flow chart of the states of the module. The module starts in the
idle state state. When new data is placed on the DATA bus addressed to the specific expansion
bus, the data is latched and the module’s state changes to the addr state state. The module stays in this state for four clock cycles and then moves to the addr ack state state. During these two states the module outputs the address of the data on EXBUS. In the addr ack state
CHAPTER 4 — FIRMWARE DESIGN FOR THE PROGRAMMABLE LOGIC DEVICES 79 idle_state addr_state data_ack_state nint_state Received Address ? Yes No data_state Received Data ? No Yes addr_ack_state RnW = '1' No Yes
CHAPTER 4 — FIRMWARE DESIGN FOR THE PROGRAMMABLE LOGIC DEVICES 80
state the module waits for a signal from the external device connected to the expansion port, indicating that it received the address. This signal is received through the nACK input. When the acknowledgement signal is received, the module moves to the data state state. If the signal was not received after 14 clock cycles, the module returns to the idle state state. The module stays for four clock cycles in the data state state and then moves to the data ack state state. During these last two states the module outputs the data on EXBUS. It waits in the data ack state state for the acknowledgement signal from the external device that it received the data. The signal is again received through the nACK input. When the acknowledgement signal is received and the transaction was for a read operation, the module moves to the nint state state. If either the acknowledgement was not received after 14 clock cycles, or it was received and the transaction was for a write operation, the module moves to the idle state state. In the nint state state, the module outputs an interrupt pulse to FPGA Main through the nINT output and returns to the
idle state state.
This chapter discussed the design of the firmware for the four programmable logic devices included in the system. The PEC33 system was tested by implementing a shunt active power filter. The theory behind the implementation, simulation results obtained with the Simplorer simulation software package and the practical results obtained is discussed in the next chapter.
Chapter 5
Test Implementation: Control of an Active
Power Filter
In this chapter the operation of the controller is tested by implementing a shunt active power filter. The first section provides an overview of the system that was implemented. In subsequent sections the basic compensation scheme and the theory behind it is explained, and the simulation model and practical implementation of the system are discussed.
5.1
Overview of the System
In Figure 5.1 a simplified block diagram of the system is shown. The system consists of three parts: the plant, the active power filter and the controller. The plant of the system is a three-phase voltage source driving a three-phase rectifier connected to the series combination of an inductor and a resistor. The load draws both real and reactive power from the source. The idea is that the filter should inject current in such a way into the system, that the reactive power supplied to the load, should come from the filter and not from the three-phase source. To achieve this the filter is constructed using three phase arms (one for each phase of the plant) connected to three filter inductors. The phase-arms control the current injected into the system through the inductors by controlling the average voltage across the inductors. The final part of the system is the power electronics controller that was developed, the PEC33. It measures the three phase currents, the voltages supplied to the three phase rectifier and the current injected into the system by the three phase arms. The PEC33 uses these values to calculate the control signals for the phase arms. The phase arms are switched using space vector pulse-width modulation (SVPWM).