The Programmable Logic Devices

The programmable logic devices (PLDs) were added to the system to make the digital logic design re-configurable. The task of the PLDs is to generate and send control signals to and receive and decode signals received from the other devices in the controller system.

The Field-Programmable Gate Arrays

Two of the EP1K50QC208 ACEX series field-programmable gate arrays (FPGAs) from Altera were used in the system. They are cheaper and faster than the older FLEX series devices.

CHAPTER 3 — DESIGN OF THE CONTROLLER HARDWARE 20 Serial2FRAM.hex Build Project Map File file.out Size of block 1 DSP Data of block 1 Destination of block 1 Size of block 2 Data of block 2 Destination of block 2 file.hex Size: 0x00000001 Data = 0x00000000 Code entry point address

Size of last block

Data of last block Destination of last block

Size of block 3

0x00000000

Dummy block

Memory width: 0x00000001

Strobe control reg. value

FRAM 0 DSP FRAM 0 Size of block 1 DSP Data of block 1 Destination of block 1 Size of block 2 Data of block 2 Destination of block 2 Size = 0x00000001 Data = 0x00000000 0x00809994

Size of last block

Data of last block Destination of last block

Size of block 3

0x00000000

CHAPTER 3 — DESIGN OF THE CONTROLLER HARDWARE 21

Figure 3.5: DSP 14-Pin Header Signals and Dimensions (figure taken from [10])

Signal Description Emulator Target

State State

TMS Test mode select Output Input

TDI Test data input Output Input

TDO Test data output Input Output

TCK Test clock of 10.368MHz Output Input

TRST Test reset Output Input

EMU0 Emulation pin 0 Input Input/

Output

EMU1 Emulation pin 1 Input Input/

Output

PD(Vcc) Presence detect Input Output

TCK RET Test clock return is the test clock input to the emulator. Input Output

GND Ground

CHAPTER 3 — DESIGN OF THE CONTROLLER HARDWARE 22

Figure 3.6: Connection of the DSP to the Emulator Header (figure taken from [10])

These devices also have the lower input/output supply voltage of +3.3V which reduces power consumption. The reason why two devices were included in the system is that one device does not have enough input/output pins available. The logic functions were divided between the two FPGAs as follows:

FPGA Main

Controls external communication channels

Controls access to the system data bus

Controls access to the FRAM

Controls the real-time clock

FPGA Analog

Sends control signals to the ADCs and processes the received data

Sends control and data signals to the DACs

Generates and outputs the PWM signals

Receives and processes PWM error input signals

Controls a standard 2-line LCD

CHAPTER 3 — DESIGN OF THE CONTROLLER HARDWARE 23

FPGAs have volatile internal memory which implies that like the DSP, the FPGAs must have a non-volatile source for its programs. One EPC2LC20 configuration device from Altera is used for this task. When the system is powered up, the EEPROM copies its data serially to the two FPGAs. Figure 3.7 illustrates how multiple FPGAs can be programmed from one configuration device with the same configuration data. The configuration setup used to program the FPGAs in the PEC33 system is based on this topology. The only difference is that the two FPGAs should not receive the same configuration data. To accomplish this, the FPGAs are connected in a data chain by connecting the nCEO output of FPGA Main to the nCE input of FPGA Analog. The first configuration file copied to the FPGAs will then configure FPGA Main. When FPGA Main is configured, it drives its nCEO output LOW, enabling FPGA Analog to be configured by the next configuration file received. The configuration device is configured using its JTAG ports with a ByteBlaster cable connected to a personal computer. A single programming file (.pof) is created and transfered to the configuration device. This file is the combination of the SRAM

object files (.sof) of the projects for the two FPGAs. To create the programming file, the Con- vert SRAM Object Files option in the file menu of the MAX+Plus II program is used. When the

first prototype for the PEC33 controller was constructed, the configuration of the configuration device worked without any problems. The only problem was the configuration device did not automatically configure the FPGAs when the system was powered up. An error was discov- ered in the datasheets describing the EPC2 configuration device. According to the datasheet, the device has user-configurable 1kinternal pull-up resistors connected to its OE, nCS and

nINIT CONF pins. The idea is that the system can either be setup to use these internal resistors,

or external resistors can be used as illustrated in Figure 3.7. In the prototype of the PEC33 system, the external resistors (of 1k) was connected, and the internal ones disabled with soft-

ware. The documentation error was that the internal pull-up resistor on the nINIT CONF

pin is always enabled and is NOT user-configurable. This meant that the effective pull-up

resistance connected to the pin was 500. It was therefore unable to drive the pin LOW to

signal the start of the configuration of the FPGAs. Subsequently the resistor was removed, and the FPGAs configured automatically without any difficulties.

The Erasable Programmable Logic Devices

One erasable programmable logic device (EPLD) for each of the two expansion busses of the system are also included. The operation of the expansion busses is discussed in section 4.4. The EPLDs used are the EPM7256B-100 in the MAX7000B series from Altera. Figure 3.8 illustrates how multiple devices (like the EPLDs) can be configured in a JTAG-chain. This is the topology used to configure the EPLDs.

CHAPTER 3 — DESIGN OF THE CONTROLLER HARDWARE 24

Figure 3.7: Device Configuration with a Download Cable and a Configuration Device (figure

taken from [14])

Figure 3.8: JTAG-Chain Device Programming with a ByteBlaster Cable (figure taken from

CHAPTER 3 — DESIGN OF THE CONTROLLER HARDWARE 25