buses Difference between memory and access Machine cycle
such as for connection to (input/output) plug-in adaptor cards. Anybody who has been around PCs for awhile will have heard of the ISA bus this is an example of such a special-purpose bus. The best starting-point is to consider the structure of the bus that is directly connected to the CPU.
First, we can analyse the CPU bus by breaking it into three logical groups of lines. Really, the bus is a big bunch of wires, with certain wires carrying the address, some carrying data, and some performing control functions this is shown in Figure 1.5 on page 13.
In fact, each of these groups is sometimes referred to as a bus in its own right.
Intuitively, you can imagine that if the CPU is to access memory, it would have to send the correct address to memory on the address bus, and the data transfer would take place over the data bus. But what about If the CPU wants to send data to an output device, for example a printer, there is the same scenario of these three buses.
The CPU has to put the appropriate address of the printer output port onto the address bus, and then the CPU will have to put the data onto the data bus.
The essential point here is that the address and data buses are being used for two different purposes. So how do the various chips that are connected to the bus know whether the current operation is an I/O-port access or a memory access? After all, they are all wired onto the same bus, as Figure 1.3 shows.
Control Bus
To understand the problem introduced above of how the bus performs access to two different kinds of chips memory and I/O it is necessary to have a closer look at the control bus. First, look at Figure 7.1. Also look at Figure 7.2.
For a memory access, say, to read the next instruction, the CPU goes through what is called a machine cycle, which simply means it reads or writes memory. There is also such a thing as a “null cycle”, in which the CPU is doing something within itself for that clock-period.
When the CPU wants to access the memory, it puts an address onto the address bus at the beginning of the cycle, then it puts ALE low to let the rest of the system know there is a valid address. Depending upon whether the CPU wants to do a read or write operation, it pulses or low. In the case of a
memory read it would send low, which tells the memory chips that they are supposed to send data to the CPU.
The memory responds by putting the data on the data bus, and the CPU reads what is on the data bus near the end of the cycle the exact moment when the CPU reads the data bus is when
goes high.
Figure 7.1: CPU bus showing some of the control signals.
CPU and associated chips
These are control signals from the CPU maybe via
associated /bufferingi s). There are also going the other way. Address bus (20 bits for 24 bits for 80286 32 bits for 80386 Data bus (8 bits for 8088) 16 bits for 8086 80286) 32 bits for 80386) Control bus
INTA Interrupt Acknowledge) ( Read)
(I/O Write)
Read) ‘(Memory
ALE (Address Latch Enable) appended to some signal names indicates they are “low active”.
Start of machine cycle End of machine cycle Time ponds to one or more clock (a machine cycle corres- CPU puts an address on address bus cycles, depending upon
which CPU)
There is still a loose end to the above description. How does memory determine which data to put on the data bus? The CPU is sending out an address asking for the data at a particular memory location. Figure 7.3 shows what the circuitry looks like at the memory end.
Figure 7.3: Interface, CPU to memory.
ALE Detects the address
Al 9
Address
range of the RAM-- Al9 chi
address bus Al
7
has the
decoder
hig er orderaddress bits as input. A l 6
RAM
Read* Write*. CS
m e a n s “Chip Select” data busAddress Decoder
Basically, a memory chip has a data bus, an address bus, chip select input(s), and read/write control input(s). This example RAM (Random Access Memory) chip has an active-low chip select line coming from an address decoder.
This decoder detects the presence on the address bus of the appropriate addresses for this particular memory chip this chip is being addressed, it “selects” the memory chip.
Note that the address decoder itself has a CS* (chip select) input ALE is connected to this. It ensures that the address decoder only operates when there is a valid address on the address bus. Assuming that the RAM is addressed correctly, the CPU tells it via
and which way the data is to go.
Notice that only Al7 to A19 go to the address decoder this is an example circuit only, and specific circuits may differ from this, but generally it is only necessary for some of the address lines to go to the decoder. This is because the memory chip resides at a range of addresses the lower order address bits go directly to the chip to select a particular memory byte.
Get the idea? The higher address lines select the chip, while the lower lines select a particular location on that chip.
BIT:
There are three address lines into the decoder in this example, Al 7
to Say that the decoder is designed to detect an input of 101 binary:
19 18 17 16 15 14 13 12 11 10 9 8 7 . . . 0
1 010 0 0 0 0 0 0 0 0 0 . ..o
This means that the RAM chip occupies address range to and the size of the RAM would have to be = 128K bytes.