Normally set “Base” is the address segment.
to zero on the of the segment.
286.
“Base+” extends the base segment addressing beyond 24 bits. “#“extends the limit beyond 64K.
The byte in Figure 1.13 has various flags and codes. It has a two-bit DPL field (Descriptor Privilege Level) that determines the privilege level of the segment. It has P (Present) and A (Accessed) bits that are used for moving the segments in and out of memory. There are R (Read) and W (Write) bits that set constraints on reading and writing the segment. There is also the C (Conforming) bit and ED. The latter is set if the segment is a stack.
I go into the description of the descriptor in far greater detail in Chapter 12.
Paging
There are two paging modes in the 386. One is built on top of the descriptor tables, and the other, called virtual-86, does away with the descriptor tables altogether.
What’s wrong with segments? Page tables and control registers Linear address
I’ll look first at the one built on top of the desriptor tables. From our program point of view it Iooks just like the segmentation mechanism with the GDT and The only difference is that the CPU secretly stores the segments in actual memory not in one contiguous chunk, but all over the place as
Why go to this trouble? The operating system has trouble bringing segments in and out of memory because they are all different sizes if a new segment is to be brought in, space must be found for it, but space released by a segment that has vacated its spot may not be the right size. This is a real problem for the operating system, and it ends up with lots of little unused gaps everywhere. Inefficiency.
By transparently parcelling the segment up into lots of little pages all the same size and storing them wherever there is a space, the mismatch of segment sizes is no longer a problem. We know that a space vacated by a departing page will be exactly the right size to take a new page. No problem.
Well, there is one. To achieve this, more translation tables are required, page tables. The CR registers are used to address these, and the page tables are kept in memory just like the descriptor tables.
The CPU has various extra registers for maintaining the paging mechanisms, most importantly, CR3, which contains the base address of the Page Table Directory.
Just for the record . . .
The address computed from the descriptor table, now renamed the linear address (as it is no longer the final physical address), is divided into fields, with bits 22 to 31 being an index into a page-table directory that gives the address of a particular page table. Bits 12 to 21 are the index into this second table, which contains the final address. Bits 0 to 11 are unchanged and become part of the final address.
You will come across the words linear address later in the book. Note that sometimes the words virtual address are used in various books to mean the same thing, though there is a distinction. The linear address is that 32-bit address that would be the physical address if page tables didn’t get in the way.
Virtual-86
This is another paging mechanism that does away with descriptor tables. It was intended to provide the 386 with better Protected mode emulation of the 86 CPU than the 286 can manage, which it does very well.
Paragraph addresses are back!
This mode is fascinating. It also does away with selectors and brings physical segment (paragraph) addresses back into the segment registers! Thus we come full circle, but with a vital difference.
Although the 16-bit segment address is back, and once more programs designed to directly manipulate segment registers can do so. The CPU does compute a 20-bit address consisting of paragraph address plus offset, but this is not put on the external address bus. Instead, it is processed via page tables, that is, translated to some other 32-bit address then put onto the address bus.
Once again, this paging is transparent to the programmer, but it does mean that the program, data, etc. are not where you think them to be judging from the segment registers.
Virtual-86 mode is useful not just for emulating the old XT computer, but is the very foundation of Windows Enhanced mode. True, each virtual machine will have an addressing limit of but Windows can create many of these (Figure 1.14).
Figure 1.14: Virtual Real mode.
Appar- ent address space. Virtual XT PC Virtual XT PC 386 PC
Instead of putting the 20-bit linear address onto the address bus, as
bits of the for Real mode, virtual-86 mode uses the upper 8 bits of this
linear address as a lookup in the current page table note that the table address are entry contains the base address of the page, which is combined remapped with the lower 12 bits of the linear address to form the actual32-bit address. It is this final address that the CPU puts out
Four privilege levels f i e l d IN, and
So what happens if your program writes directly to video RAM at segment This is up to the operating system, which most likely will create screens for each task, setting them up anywhere it wants to in