System Controller

The CLIP7A system is microcode controlled and horizontal microprogramming is employed. Each micro-instruction consists of 160 control signals which operate both the linear array and the controller. The system controller consists of a microcode sequencer and a microcode programme store. The controller, however, also acts as an interface between the linear array and the host computer. The system controller occu­ pies six locations in the host’s VME bus address field. Two locations are employed for data input/output and the remaining four are used for control and feedback signals. The structure of the controller is depicted in Fig. 4.9. The controller can be divided into three functional units: an interface unit, a computing unit and a microengine.

The Interface Unit

The interface unit enables the controller to communicate with the host and the array. The unit includes two 16-bit pipelined data channels called the TO-pipe and the FROM-pipe. The channels are uni-directional and the host will only write to the TO- pipe and read from the FROM-pipe. In the original design the two pipes are imple­ mented by 16 word deep First-In-First-Out registers. Each pipe comprises of 2 regis­ ters arranged in series so that up to 32 words of data can be stored. Data passes through both registers before reaching its destination (either to the array or the host). The registers in a pipe must be synchronised so that data can be transferred from one register to the other. In the original circuit, there was a problem in synchronising the registers and data were lost when moving from one register to another. The problem was resolved by a new design employing a single device that can store up to 512 bytes of data. The new design also provides more data storage so that either the array, or the host, can insert more data to the pipes before they are full.

Interface Unit CBus To Pipe From Pipe AM29116 RAM HOST Microengine Interface Registers The CLIP7 Array Computing Unit

Communication between the controller and the array is through five 16-bit regis­ ters. The registers comprise: a data register, Dbus register, serial register, position register and connect register, and their functions are:

Data: for sending RAM addresses to the array. The output of the register is connected to the co-processor’s data bus. At each operation only 8-bits are transferred because the address bus of the PE is 8-bit. A control signal determines whether it is the high byte or the low byte of the register that is broadcast.

DBus: for sending data to, or receiving data from the array. The high-byte of the register is connected to the processor’s D-chain, whilst the low-byte is connected to the co-processor’s D-chain.

Serial: for serial data transfers between the array and the controller. Serial data input to this register from the array is derived from the encoding network, whilst the output is used together with the Position register to send data to a selected PE in the array.

Position: used in conjunction with the serial register. It can be loaded either by the host or the linear array. The value loaded by the array is the position of the first non­ zero processor (determined according to the data stored in a PE’s Nout register). An address written by the host specifies the location of the PE for inputting data serially from the Serial register.

Connect: the value of this register will define the connectivity of the array. It con­ trols the Dbus edge connectivity and globally defines the value of the label for the Nin register.

The Microengine

The microengine includes a microcode sequencer (an AM29331) and a micro­ code programme store of 16Kxl60 bits. The programme store is loaded during system initialisation and the microcodes control the operations of the array, the computing unit and the microengine itself. Operations of the sequencer are controlled by 64 instructions including conditional branch and looping.

The Computing Unit

The Computing unit consists of an AM29116 processor, which is a 16-bit microprogrammable processor, and 64 Kwords of memory. Because the system is a linear array only a single row of an image is processed at each operation. In order to process the entire image a single operation, or a group of operations, must be repeated, proportional to the size of an image. As the instruction stream comes from the host it implies that the rate of communication between the host and the controller must be very high. The function of the computing unit is first to store the instruction stream which is going to be repeated in the coming operation in its RAM. The instruction stream instead of being issued by the host now comes from the computing unit thus reducing the demand for a high communication rate between the host and the con­ troller. This arrangement improves the system’s performance.