The Alpha 21064 microprocessor is the largest and fastest chip built using the CMOS-4 technology. Careful analysis of this chip determined the number of vias and the total length of lines (as a function of
Digital Tecb11ical ]om-nal Vol. 4 No. 2 Spring 1992
Electromigration Reliability of VLSJ Interconnect
l ine width) that carry currents near the electro migration design rule limit. Interconnects with currents much less than the design rule li mit have negligible impact on the electromigration reliabil ity. With this information, we can then calculate the appropriate performance requirements for the test structures to meet our chip reliability goal.
Our reliability goal is to assure a less than 1 per cent probability of chip fa ilure in 10 years under worst-case operating conditions. The stress accel
eration model described in equation (1) is used to extrapoLate from accelerated stress conditions to worst-case operating conditions. Scaling of test data to the chip level is accomplished by use of the mu ltilognormal approximation to the failure distribution.
The entire circu it can be considered to consist of several component groups, where each group includes a particular type of interconnect element, e.g. , a certain via type or line wid th. The lognormal unit failure distribution for the ith group F1 (t) is characterized by y1 and
()1 .
Rewriting equation (8) in a slightly more compact form, the cumu lative probabil ity of chip failureH(t) = 1 - I1S1 (t)
I (9)
where
(10)
and N1 is the number of components from the ith group on the chip. For vias, N1 is the number of vias; for l ines, N1 is the total length divided by the characteristic unit length, which depends on line width. Since the reliability goal is for H(t) to be less than 0.01 for 10 years under worst-case operating conditions, then for each group, F;(t) is much less than 0.01.
As mentioned previous ly, u ncertainty in the values for y,
e,
and l stems from the uncertainty inherent in estimating t50 and CT to a given level ofconfidence from experimental data. It is illum inat ing to examine the impact of this inherent uncer tainty has on the performance requirements for the test structures to meet the chip reliability goal .
Consider the simple case of only one component group, namely a single l ine width. The required test structure t50.test relative to the time until 1 percent cumulative failure for the chip occurs t01.chip is plot ted in Figure 9. This ratio is graphed as a function of the ratio of the number of units in the test struc ture to that of the chip, Nres
/
Nchtp' for a given combi nation of Nrest and y. For this illu stration, we useSemiconductor Technologies
CURRENT DENSITY (mA/I-'m2)
[==:J
ff$%1
0.235 - 5.244 5.244 - 1 0 . 254 1 0 .254 - 1 5 . 264 TEMPERATURE INCREASE ("C)-
11111111111111
1 .836 - 1 .9 1 5 1 .9 1 5 - 1 .993 1 . 993 - 2.072111111111111
1 5.264 - 20.274-
20.274 - 25.283(a)
2.072 - 2. 150[==:J
2 1 50 - 2.229(b)
-� -··1 ..Figw·e 7 Finite Element Simulations of Current Density and Temperature Distributions in 7itngslenjilled Vias
Figure 8 Secondary Electron Micrograph
of Electromigration Damage at a Tungsten jilted Via
points from the example shown in Figure 4 for com
parison.
Points A and c both l ie on the edge of the al lowed
parameter space in Figure 4, but y and N are both
larger for C. Figure 9 shows that the requirements
on t50, ,est are greater for C than for A. However,
the relative effect of increasing N o r y separately is
not clear. Increasing N alone, that is, comparing
point Bl to A, actually results in a decrease in the
test requirements, as shown in Figure 9. This effect
weakens as the N1e5/Ncbip' ratio approaches unity.
Thus, the test l ine shou ld be as long as practical to mitigate the impact of uncertainty in /. The increase in t5o, tes/t01,,bip' therefore, is a result of increasing y.
The sensitivity to increasing y alone can be seen in
Figure 9, by comparing point 82 to A.
To assure that the chip rel iabil ity goals are met, the most conservative combination of parameter estimates shou ld be used . These val u es are the most stringent in setting and meeting the test per formance requirements. The most rigorous test per formance requirements are set by using the largest possible value for y. In the example presented i n Figure 9, this value o f y impl ies the l argest value of
N, i.e., the smal lest value for l, within the ranges
Digital Technical journal Vol. 4 No. 2 Spring 1992
Electromigration Reliability of VLSJ lnterconnect
a. £� ;; � 1 03 1 02 1 0 KEY: --B- -y = 1 .5, N = 1 0 Nresr/Nchip -8- -y = 1 .5, N = 200 --v- -y = 2.09, N = 1 0 -B- -y = 2.09, N = 200
Figure 9 Requirements on t,0 for the Test Structure Relative to t01 for the Chip as a Function of the Ratio
of the Number of Elements in the Test Structure to That of the Chip
set by the confidence limits on cr and t50 . The most
stringent criterion for meeting the test perfor mance requ irements is to use the lower limit of the
confidence interval for t50 from the test data, which
corresponds to the minimu m e val ue consistent
with the values of y and N.
Electromigration l ifetimes, and thus the scal ing model parameters, are a sensitive function of the microstructure of the conductor film . t9 Therefore, si nce the effect of normal microstructural varia tions cannot be u nambiguously determined a pri ori, a number of lots must be tested to assess the effects of lot-to-lot variations.
Each lot undergoes a statistical test of the hypothesis
H (10 years) :os 0. OJ (11)
where H(IO years) denotes the cumulative proba
bil ity of chip failure in the first 10 years of continu
ous operation under worst-case conditions. To pass the test, the probabi l ity of accepting the hypothesis
when H(lO years) is greater than 0.01 must be less
than 0.1 . This criterion gives at least 90 percent
confidence that a test group passing the statistical test, i.e., for which the hypothesis is accepted,
Semiconductor Technologies
• Does indeed come from a lot that meets the
requirement of not failing more than 1 percent of the time in 10 years
• Is not a statistical fluke
The statistical analysis procedures used to imple ment this model in the electromigration qualifi cation testing are coded in a software tool. The software extracts the most conservative MLN model parameters from the failure-time distribu tion measured for every type of structure tested for each lot. This tool can be used to perform the statis tical test just described to verify that the rel iability goal has been met.
Summary
Interconnect electromigration rel iability becomes inc reasingly important with each step in the evolu tion of CMOS technology. Therefore, it is necessary
to rigorously characterize the various components of the circu it metall ization and to develop depend able models to relate test device data to long-term chip reliability.
We have presented a scaling model for relating the resu lts of accelerated electromigration life tests on test structures to the overall chip reliability. This model was used as the basis for formulating qual ifi cation requirements for electromigration reliability assurance of the CMOS-4 process technology and the Alpha 21064 microprocessor.
Acknawledgments
We would like to acknowledge the contributions of the fol lowing individuals: Barbara Miner, Steven Bill, and Jamie Rose for TEM work, Aldo Pelillo for FIB/SEM work, Ahsan Enver for finite element simu lations, john Kitchin, Bill Martin, Dave Dunnell, Dave Foggo, Terry Spooner, Lesley Elliott, and Profes sor Carl Thompson of the Massachusetts Institute of Technology.
References
1 . T. Kwok and P. Ho, "Eiectromigration in Thin Films." Diffusion Phenomena in Thin Films and Micmelectronic J\t[aterials, edited by D. Gupta and P Ho (Park Ridge, New jersey:
Noyes Publications, 1988): 369-431, and the references therein.
2. P. Ghate, " E lectromigration-induced Failures in VlSI Interconnects," Proceedings of the
1 24
Twentieth A nnual International Reliability Physics Symposium ( 1982): 292- 299.
3. H. Schafft, T. Staton, ]. Mandel, and J. Shott, " Reproducibi lity of Electromigration Mea surements," IEEE Transactions on Electron Devices, vol . ED-34, no. 3 (March 1987): 673 -680.
4. M. Shatzkes and ]. Lloyd, "A Model for Con ductor Failure Considering Diffusion Con currently with Electromigration Resulting in a Current Exponent of 2," journal of Applied Physics, vol. 59, no. 11 Oune 1986): 3890-3893.
5. ]. Black, " Mass Transport of Aluminum by Momentum Exchange with Conducting Elec trons," Proceedings of the Sixth A nnual Inter national Reliability Physics Symposium (1967): 148- 159.
6. B. Argarwala, M. Attardo, and A. Ingraham, " Dependence of Electromigration-induced Failure Time on Length and Width of Alu minum Thin-film Conductors," journal of Applied Physics, val . 41, no. 10 (September
1970): 3954-3960.
7. ). Lloyd and J. Kitchin, "The Electromigration Failure Distribution: The Fine Line Case,"
journal of Applied Physics, vol. 69, no. 4
(February 1991): 2117- 2127
8. S. Vaidya, D. Fraser, and A. Sinha, "Electro migration Resistance of Fine-line AI for VlSI
Applications," Proceedings of the Eighteenth A nnual International Reliability Physics Symposium (1980): 165 - 170.
9. E. Kinsbron, "A Model for the Width Depen dence of Electromigration Lifetimes in Alu minum Thin-film Stripes," Applied Pbysics Letters, vol. 36, no. 12 Oune 1980): 968-970.
10. ). Cho and C. Thompson, "Grain Size Depen dence of Electromigration-induced Failures in Narrow Interconnects," Applied Physics Letters, vol. 54, no. 25 Oune 1989): 2577-2579.
1 1 . D. Walton, H. Frost, and C . Thompson, " Com
puter Simulation of Grain Growth in Thin film Interconnect Lines," Materials Research
Society Symposia Proceedings, vol. 225
(1991): 219-224.
12. E. Arzt and W Nix, "A Model for the Effect of Line Width and Mechanical Strength on Electromigration Failure of Interconnects with ' Near-bamboo' Grain Structures," jour
nal of Materials Research, vol. 6, no. 4 (April
1991): 731 -736.
13. I. Blech, " Electromigration in Thin Aluminum
Films on Titanium Nitride," journal · of Applied Physics, vol. 47, no. 4 (April 1976):
1203- 1208.
14. E. Atakov and ). Clement, "Electromigration Failure Time Distribution: Scaling from a Test Structure to the VLSI Chip," Proceedings of
the Ninth VLSI Multilevel Interconnection
Conference (1992): 366-371 .
15. M. Garver et al., "CMOS-4 Back-end Process Development for a VLSI 0.75 -J.Lm Triple-level Interconnection Technology," Digital Tech nical journal, vol. 4, no. 2 (Spring 1992, this issue): 51 -72.
Digital Technical journal Vol. 4 No. 2 Spring 1992
Electromigration Reliability of
VIS/
Interconnect16. F. Matsuoka et al., " Electromigration Reliabil ity for a Tungsten-filled Via Hole Structure," IEEE Transactions on Electron Devices, vol. ED-37, no. 3 (March 1990): 562-567.
17. H . Rathore, "Via Resistance as a Technique to Control the Electromigration of Non-overlap Via Holes," Proceedings of the Twentieth A nnual International Reliability Physics
Symposium (1982): 77-80.
18. ]. Estabi l, H. Rathore, and F. Dorleans, "The Effect of Metal Thickness on Electro migration-induced Shorts in Submicron Tech nology," Proceedings of the Twenty-ninth Annual International Reliability Physics
Symposium (1991): 57-63.
19. P. Smith, ). Lloyd, and G. Prokop, "Lot-to-lot Variations in Electromigration Performance for Thin Film Microcircuits;' journal of
Vacuum Science and Technology, vol. A2,
no. 2, (April-June 1984): 220- 223.