The extrapolated threshold voltage for an n-channel device plotted as a function of gate length is shown

in Figure 8. Excellent threshold voltage control

is shown for channel length down to 0.5 JLm. The

n-channel drain current,

Ids,

is plotted in Figure

9

_as

a function of drain voltage, Vds' while �s is varied

from

0

_to

5 V

_with

0.5-V

_{steps. In Figure}

10,

_{the drain}

current is plotted on a logarithmic scale as a func­

tion of gate voltage to highlight the subthreshold

CMOS-4 Technology for Fast Logic and Dense On-chip Memory

�

:J

0.60 0.58 0.56 0.54

6

0.52 0 0.50 0.48 0.46 0.44 0.42 0.40 0.6 1 .0 1 .4 1 . 8 2.2 2.6 3.0 Lelf(�m)

Figure 8 N-channel 17Jreshold Voltage Plotted

as a Function of Effective Channel

Length 7.0 6.0 5.0 <(

.s

4.0 !/) .9 1 . 0 0 1 .0 Figure 9 2.0 3.0 4.0 Vos (V) 5.0 6.0

N-channel Drain Current Plotted

as a Function of Drain Voltage

7.0

slope behavior for

�ts

of OJ V and 3.6 Y. The sub­ threshold slope was measured to be 86 mY per decade and is characterized by good drain-induced, barrier-lowering characteristics. The drawn dimen­ sions of the transistor are 12.5 J-Lm wide by 0.75 J-Lm long.

Similar characteristics are observed for the

p-channel device and are shown in Figures 1 1 , 12,

and 13. The subthreshold current conduction and

punch-through characteristics are very similar to those of the n-channel device.

Digital Technical journal Vol. 4 No. 2 _Spring 1992

1 0-2 1 0-5

�

_9

1 0-8 10-1 1 1 0-1 4 -0.5 0 0.5 1 .0 1 .5 VGs (V)

Figure

10

N-channel Drain Current Plotted

as _{a Function of Gate Voltage}

2.0

Table 3 shows typical CMOS-4 transistor process

and device parameters. The j unction depths, xi'

and the n-well depth, _Xweli' are simu lated with the

SUPREM process simulator and verified with SIMS

analysis. Tax is the physical gate oxide thickness; Vrx

is the extracted threshold voltage; Lcrr is the nomi­

nal final channel length, and delta L and delta w are electrically extracted using the Terada method, which accounts for the parasitic series resistance.

Idsat is the saturation current measured with the

drain and gate voltage at 3.3 _V BVDSS is the punch­

through voltage measured with

�s

set at 0 Y.

Silicided Interconnects Characteristics

Table 4 shows the effects of the sal icide process on the parasitic resistance in four consecutive tech­ nologies. The CMOS-1 process uses no sil icided gate or drain and therefore is expected to have a high interconnect sheet and contact resistance. CMOS-2,

on the other hand, uses a low sheet tungsten sili­ cided (WSi2) polysilicon gate with a sheet resistance of 3 ohms per square. The CMOS-3 and CMOS-4 tech­ nologies use sal icided low sheet resistance CoSi2 for both the polysil icon gate and the source/drain region with a sheet resistance of 5 ohms per square.

SRAM Implementation

A six-transistor (61) cell was selected for its process simplicity and cell stabili ty. To provide a dense , cost-effective SRAM capabil ity, the 6T cell was

Semiconductor Technologies 0.60 0.58 0.56 0.54

�

0.. _0.52 >-- > LJ.J f- 0.50 :::> _J 0 (/) 0.48 co <( 0.46 0.44 0.42 0.40 0.6 1 . 0 1 .4 1 .8 2.2 2.6 3.0 Len (�m)

Figure

11

P-chcmnel Threshold Voltage Plotted

as u Function of rffective Channel Length -3.0 -2.0 - 1 . 0 -1 .0 - 2 . 0 - 3 . 0 -4.0 - 5 . 0 - 6 . 0 -7.0 Vos (V)

Figure

12

P-channel Drain Current Plotted as u Function of Drain Voltage chosen over the 4T cell, which requires complex, two-level polysilicon films.

During the initial 6T cel l process development, the TiN local interconnect scheme was considered advantageous to the buried contact scheme. In the buried contact procedure, the gate oxide is pat­ terned and etched, and then a polysil icon gate is deposited to provide the contact between poly­ silicon and the active area. This technique a llows the polysilicon ti.lm to access the source/drain

48

/

-1 o-14

VGs (V)

Figure 13 P-channel Drain Current Plotted as a Function o{Gate Voltage region without the need for area-consuming met:�l contact. Unfortunately, this technique is not readily compatible with symmetric n + and p+ doped poly­ silicon structures. In addition, sil icon grooves might form during polysilicon etch, which could jeopardize the junction integri ty and cause leakage or short circu its to the silicon substrate.

The preferred method to access the source/drain region was the use of TiN strap over CoSi2. TiN local interconnect is a conductive material. When it is sputter deposited on the wafer, pattern and etch can be used to strap the node of one transistor to the gate or drain of another transistor. Also, the TiN local interconnect provides excel lent etch selectiv­ ity to the umkrlying CoSi 2 material . The TiN local

interconnect process proved superior to the buried contact scheme because the improved etch selec­ tivity to CoSi2 prevents junct ion leakage.

In standard layout techniques, the metal 1 con­ tact is spaced 0.75 JLDl from the edge of the polysilicon gate and the isolation. This spacing results in a 2.25-t-tm wicle act ive area, as shown in Figure 14a. In contrast, the local interconnect tech­ nique does not require a contact region; therefore the active area width can be scaled to 1 .5 t-tm, as shown in Figure 14 b. The usc of local interconnect has reduced the

61'

cel l area from 120 JLlll2 (no Ll) to 100 t-tm2 (with

LI).

In addition, the use of LI has improved yield due to a relaxed metal 1 contact

requ irement and metal spacing.

CMOS-4 Technology for Fast Logic and Dense On-chip Memory

Table 4 Sheet Resistances for CMOS Techno log ies (Ohms per Squa re)

Sou rce/drain sheet resistance Polysilicon sheet resistance

In document dtj v04 02 1992 pdf (Page 48-51)