Figure 6
feedback Loop Compensation
to relax the jitter specitication ti·om 25 ps to 70 ps RMS, and there were some difficulties getting good load balance . The specitication did not change, how ever. Reassessing the al located bus settling time yields the following:
Bus cycle
Transmitting module (Teo) Setup and hold time for the
receiving mod u le Clock skew
Time allocated for bus settling
1 5 .0 ns 5 . 1 ns
1 . 5 115 2 . 2 ns
6.2 ns
SPICE simulations tor a fully lo;�ded bus with the worst possible driver receiver position yielded a bus settling time of 5 . 7 ns. The relaxed skew of 2 . 2 ns maximum was acceptable tor the design .
Comparative Analysis
A comparison of clock distribution systems between two other p latforms best summarizes the AlphaScrver
4 100 system. The AlphaServer 4 100 has a price and
performance target berween those of the AlphaServer
2 100 and the AlphaServer 8400 systems. Table 4 com pares the basic difrerences among these systems relat ing to clock distribution tor a CPU module ti-om each platform .
Both the Alp haServer 2 100 and the AlphaServer
8400 systems have large custom AS!Cs f(x their mod
ule's bus interface. The AlphaServer 4 1 00 and the AlphaServer 8400 systems have bus termination; the Alp haServer 2 100 system does not. Allowing a bus to
46
Ta ble 3
Worst-case Clock S kew
Stage Motherboard I n puts to modules Module to module I n puts to rece ivers I n puts to receivers Tota l clock skew
Table 4 Source Out-to-out skew Load m ismatch PLL process Load mismatch PLL j itter
Clock D istri bution Comparison of Three Platforms AlphaServer 2 1 00 System
B us width 1 28 + ECC
B us speed 24 ns
Clock skew 1 . 5 ns
Inputs req u i r i n g cl ocks 1 0 Clock d rivers used 1 2
N u m be r of c l oc k phases 4
settle natura l ly (with no termination), as in the case of the AlphaServer 2 100 system, req uires a tighter skew budget from the clock system. The trade-off is higher cost, power, and PWJ3 area t()r lower bus speed . Higher performance systems, such �lS the AlphaServer 8400 and AJphaServer 4 100 systems, generally requirc bstcr bus speeds with terminators. The AJphaServcr 4 100 has shorter bus stubbing ( module transceiver to connector dispersio n etc h ) Jnd slower bus speed than the AlphaServer 8400, which allows larger skew ( Js a percentJge of the bus spccd ) .
Table 5 i s a comparison o f board areJ needed and cost for the clock syste m . Dcsigncrs analyzed an entry levcl system consisting of one CPU module, one mem ory module, and one 1/0 bridgc or interface mod u l e . Thc board area shows the spacc required b y t h e active components only ( the digitJ I p hase-loc ked l oops, PLLs, drivers, etc . ) .
Both Tables 4 a n d 5 show that the clock system dcsign t(>r the AJphaScrvcr 4 1 00 system req u ires only one-third the space of either thc Alp haServer 2 100 systcm or the AJphaServcr 8400 system at a fraction of thc cost and distributes more copies of the clock.
Ta ble 5
Board U t i l i zation and Cost Compa rison
Board a rea used* Normal i zed cost
AlphaServer 2 1 00 System 352.8 sq uare ce ntimeters 1 .00
Skew Component
500 ps (vendor specification)2 1 00 ps (si m u l ati on/bench test) 1 , 000 ps (vendor specification)'-
200 ps (si mulation/bench test)
400 ps (eight t imes the vendor specification)2 2,200 ps = 2.2 ns
AlphaServer 4 1 00 System Alpha Server 8400 System
1 28 + ECC 256 + ECC 1 5 ns 1 0 ns 2.2 ns (max.) 1 . 1 ns (max.) 25 14 1 3 1 1 Conclusions
An etkctive, low-cost, high-pcrh>rmance c lock distri bution system can be lksigncd using an off.the-shclf componcnt as the basic b u i lding block. D fG fTAL
AJ phaServer 4100 s�·stem dcsigncrs accomplished this by optimizing the bus and den: l oping simple tech niqucs structured i n the t()rm o f dcsign rules. Thcsc ru les arc
• Use positive edges t(x critical clocking.
• Match dclay through diftCrcnt connectors usmg
appropriate pinning.
• Usc a fixed dispersion ctch length from the connec tor to the PLI ,.
• Route and balance all dock nets on the same PWB
laycr.
• Minimizc adjaccnt- laycr crossovcrs and maximize spacmgs.
• Use minimum valuc tcrminarors.
• Usc tree and loop comrxns<ltion where needed . • Usc conservative local dccoupling and a low-pJss
ti l ter on the PLL ( analog powcr).
Alpha Server 4 1 00 System 1 1 1 .4 sq uare centimeters 0.46
Alpha Server 8400 System
37 1 .3 square centimeters 4.40
*Note that these measu rements do not include decoupling capacitors and terminators.
The worst-case lab measurement of clock skew between any two mod ules in a rLd ly con hgu red system was l . l ns, which is wel l within the 2 . 2 ns calculated mJximum skew.
Acknowledgments
Terry Skrypek and Bruce Al ford assisted with the prototyping and measurements. Cheryl Preston , Andy Koning, Steve Coe, George Harris, and Larrv Derenne worked with the designers to ensure compliance with the signal integrity r u les. Darrel Donaldson, Don Smelser, Glenn H erdeg, Jnd Dan Wissel ! provided invJi uablc technical guidance. Note and References
I . Sl'ICE is a genera l - p u rpose circuit simu lc1tor program
devel oped Lw Lawrence Nagel and E l l is Collen of tile \)epclrtmcm of Elecnical Engineer i ng and Com puter Sciences, Unive rsity ofCalirornia at Berkeley.
2 . CDC- Clock Distribution Circuits, Data .Book ( Dallas, Tex . : Texas Instru ments I ncorporated, 1 994 ) .
3 . A lpha 2 ! 164 /Vlicroprocessor 1-fctrdware Heference /vlmwal ( Maynard, Mass . : D igital Eq uipmem Corpora tion, September 1 994 ).
4. C. C u iks, f:"t ·etything Vou l:"uer Wanted to Know A h(mt Laminates. . But \h're Aji-aid to As/,o, 4th ed.
( Maitland, fla . : Arion, Inc., Jan uary 1 989).
Biography
Roger A. Dame
A pri ncipal signal integrity engineer in the !VI id r<lllge Servers group, Roger Dame is c u rremly worki ng on the AlphaServer 4 100 project. D uring the I 0 years he has been with this grou�), he has also contri buted to the VAX 6000, VAX 5800, VAX 7000, DEC 7000, and D EC 1 0000 proj ects. I n earlier work at DICITAL, in the Industrial Products group, he developed cmalog-to-d igital process control sys tem i ntcrr:tces. Roger joined DICITA.L in 1 97 1 . He holds an A .S . E . E .T. degree fi·orn Spri ngfield Tcclmical Cornmu
nitv College and a B.S.E.E .T. (summa c u m !Jude) fi·om Ccnrral Ne'' England College. Roger is coinventor of the laser bus used i n the DEC 7000 and DEC 1 0000 systems.