MEASURED PERFORMANCE THEORETICAL PEAK PERFORMANCE

Figure 1 1

Comparison of Al phaServer 4 1 0 0 _PI_{O Pertormancc with Theoretical 32-byte Burst Peak Perfo}r_mance

map device add ress space on i ndependent peer PCI

buses ro permit direct peer transactions. Reordering of transactions in queues on the PCI bridge, combined witb the use of PCI delayed transactions, provides a dead lock-free design tor peer transactions. Bufrers and prdetch logic that support very large bursts without stalls yield a system that can amortize overhead and deliver performance limited only by the PC! devices used in the system.

In summary, this system meets and exceeds the per­ formance goals established for the I/0 su bsystem. Notably, I/0 subsystem support for partial cache line writes and for direct peer-to-peer transactions signifi­ cantly improves efficiency of operation in a M EMORY C HAN NEL cluster system.

Acknowledgments

The DIG !Ti\L AlphaServer 4100 IjO design team was responsible f()r the I /0 subsystem implementa­

tion. The design team i ncluded Bill Bruce, Steve Coe, Dennis Hayes, Craig Keefer, Andy Koning, Tom McLaugh lin, and John Lynch. The I/0 design veri n­

cation team was a lso key to delivering this prod uct: Dick Beaven, Dmen·o Kormeluk, Art S inger, and Hitesb Vyas, with CAD support f!·om Mark Matulatis and Dick Lombard .

Several system team members contributed to inven­ tions that improved product performance; most notable were Paul Guglielmi, Rick Hetherington, Glen Herdeg, a nd Maurice Steinman . We also extend thanks to our performance partners Zarka Cvetanovic and Susan Carr, who developed and ran the gueujng models.

Mark Shand designed the PC! Pamette and pro­ vided the ped()fmance measurements used in this paper. Many thanks for the nights and weekends spent remotely connected to the system in our lab to gather this data .

Digital Technical journal Vol. 8 No. 4 1996

References and Note

l . Wimer _{U N I X Hot Iron A\\'a rds, U � I X EXPO Plus,} October 9, 1 9 96, http:/ /WI\w.aim .com (Menlo Pcnk, Calif. A I M Tech nolog\' ) .

2 . R. Cil lett, ",v!H·lORY CHAl,NEL Net11 0rk t()l" P C ! , " /f:Ff: Jiicro ( FcbruarY _{! 996 ) : 1 2- 1 8 .}

3 . G . Herdcg, " Design and I mp l e mentation of the

AlphaSen·er 4100 _{CPU and Memorv A rch itecw re,"}

Di.�itul Tech nical }oumal. vol . 8, no. 4 ( _{1 996, this}

issue ): 48-60.

4. _{PC! Local Bus Specification, Ret'ision} 2. 1 (_Portland,

Oreg . : PC! Special I nterest _{Group, I 99 5 ).}

5 . In PC! terminology, a master is _{any device that arbi trates}

for the bus _{and i nitiates transactions on the PC! ( i . e . ,}

pe_{dorms DMA ) before accepting a transaction} a s _target. Biographies

Samuel H. Duncan

A consultant enginee1· and the architect _{for the AlphaServer} 4 1 00 _{1/0 su bsystem design, Sam Du nec1n is cur}r_em_ly working on core logic design and architecwre for _{the next} generation of Alpha servers a n d _{workstations. S i nce join­} ing D I G ITAL in I 979, he has been part ofAl plu and VAX svstem engineering teams and has re_pr_esente_{d DICITA I .}

o n scvcrc1l indu_stry s tandards _{bodies, i ncludi n!J, t h e PC!} Spccic1 l Interest Gwup. He also chaired _the group that

dcl'e l oped the I EEE Sr:111dard for Com municHing Among ProCl:ssors and Periphera ls Using Shared tV!cmon·. He Ius b_{een a11·ardcd one pcuenr and has fo}ur patems fi l ed tc)l"

i 1m: ntions in the AlphaSerl'er 4 l 00 _{S\'Stem . Sam rccci,·ed} a B.S. E.E. fmm Tu fts U n i,·ersitv.

Craig D . Keefer

Craig Keefer is a principal hardware engi neer whose engi­ neering experrise is designi ng gate arrays. He was the gate array designer for one of the two 2 3 5 K CMOS gate arrays in the AJphaServer 8200 system and the team leader for the comn1and and add ress gate array i n the AJphaServer 8400 l/0 module. A member of the Server Product Development Group, he is now responsible for designing gate arrays for h ierarch ical switch h u bs. Craig joined DIG ITAL in 1 977

and holds a B.S.E.E from the U niversity of Lowel L

Thomas A. McLaughlin

Tom McLaughlin is a principal hardware engineer work­ i ng in D I GITAL's Server Product Development Group . He is currently i nvolved with t h e next generation of high­ end server platforms and is focusing on logic synthesis

and ASIC design processes. For the AJphaServer 4100

proj ect, he was responsible for the logic design of the l/0 subsystem, including ASIC design, logic synthesis, logic verification, and riming verification. Prior to joining the AJphaServer 4 100 project, he was a member of Design

and Applications Engineering within D I GITAL's External Semicond uctor Technology Group . Tom joi ned D I GITAL

in 1 986 after receiving a R T E.ET from the Rochester I nstitute ofTechnology; he also holds an M.S.C.S. degree ti·om the Worcester Polytechnic Institute .

Design of the 64-bit