Chapter 5 presents an approach to decompose the measured DUK variation into regional, system- atic, and random variation. It uses a simple model of the delay to perform this decomposition. Even with this simple model, it is able to do a meaningful decomposition, discovering several aspects of the variation within the Cyclone III FPGA. Nevertheless, this is just the beginning of the type of analysis that will yield very useful information for both FPGA manufacturers and users. Several aspects will improve the decomposition.
Primarily, a better understanding of the FPGA architecture will allow the separation of design variation from process variation. As a simple example, knowing that a particular wire index in the FPGA is slower due to design variation or process variation has very different implications. As a user, in both cases we may choose to avoid that wire. As a manufacturer, if it is slow by design, it is likely the CAD tools know of this and adjust accordingly. Moreover, the decomposition analysis can take this into account and adjust the wire delay to find the true process variation of the wire. On the other hand, if it is previously unknown process variation, it is possible that a design adjustment may mitigate this. Otherwise, the CAD tool timing models could be modified
to account for the delay difference [89].
Another improvement lies in the delay model. DUKs are composed of multiple physical re- sources, the delay model we use is only an approximation of the delay. Better matching the delay model to the individual structure of the different DUKs would allow for a delay decomposition below the DUK level. For example, if the delay of a DUK is modeled as the addition of the delay of a resources wire and a LUT, it may be possible to better separate the variation from the two components.
Finally, as we point out in Section 5.4, the decomposition is only as smart as the parameters we feed it. That is to say, if we fail to consider correlation to some parameter, it is unlikely that our decomposition will discover this correlation on its own. For example, as wires traverse the FPGA, it is possible that their physical position in the wire bundle may shift, while its logical wire index remains fixed. Thus a wire with index 9 in one region of the FPGA may share more characteristics with a wire with index 4 in another region of the FPGA, instead of the one with index 9. Our current decomposition is unable to detect this kind of correlation. A more complex decomposition that discovers new correlations would be required. Machine learning algorithms may be appropriate for these kinds of discoveries.
Chapter 7
Conclusions
Timing Extraction decomposes an FPGA into individual Discrete Units of Knowledge (DUKs). Using only resources within the FPGA, it measures the delay of a minimal set of paths, and uses their delays to compute the delay of each DUK. DUKs can then be composed to compute the delay of any path in the FPGA between two registers. A simple modification to the circuit graph allows conventional routing algorithms to perform component-specific mappings, where logic is custom mapped to best fit a given FPGA, using the computed DUK delays. It also provides the measurements needed to analyze the variation in the FPGA, and decompose it into correlated variation and random variation.
We implemented Timing Extraction for the Altera Cyclone III 65 nm FPGA, and applied it to 18 FPGAs. For each, decomposing logic blocks and the general interconnect network into 1,356,182 individual DUKs. This required running 232,250 bitstreams on each FPGA, to measure the 2,736,556 necessary paths. Our decomposition revealed ten different DUK types, each representing a different structure of the FPGA. Together these DUKs allow us to compose any path between two registers.
We demonstrate how Timing Extraction is agnostic to the structure being decomposed, and can well handle large resources as black boxes, or given their structure, can decompose the circuit further. We explore the effects of lowering the supply voltage, a common approach for energy re- duction. Our results confirm the modeling equations by showing that delay and variation increase as supply voltage decreases. We also compare our measured results to the timing models shipped with the manufacturers CAD tools. Though aware of some variation between resources, our mea- surements reveal variations not modeled by the CAD tools. This is due, in part, to the existence of random variation in the FPGA. Lastly, we demonstrate that we can repeatedly measure and compute DUK delays, and consistently reach the same results.
the physical coordinates of a DUK, systematic variation, correlated to a descriptive parameter of the DUK, and uncorrelated random variation. Our analysis reveals a distinct regional delay gradient where, over a range of 50 ps, slow resources on the top left give way to faster resources on the bottom right. The systematic correlations demonstrate differences such as horizontal wires being, on average, at least 30 ps faster than vertical wires. It also reveals a directional preference where wires going right or up are, on average, 20 ps faster, compared to wires going left or down. Finally, our random variation analysis clearly demonstrates that general interconnect resources encounter grater random variation than logic blocks. With general interconnect experiencing