Variation Sources and Physical Effects

The simplified glimpse into the manufacturing process above should serve to illustrate the com- plexities a wafers undergoes during the manufacturing of an integrated circuit. Each step must be carefully prepared and executed and each step provides variation an opportunity to infiltrate the process. In this section, we examine how variation in the manufacturing of a circuit leads to physical deviations from the design parameters of the transistors and wires being created. The next section will connect these physical variations to electrical changes in the devices.

Although there are many sources of process variation, ultimately, they manifest in two physical aspects of the devices: Geometry, and dopant concentration fluctuations. What’s more, the variation can be random, where a stochastic model best represent the physical results, either because it is a random process, or because the process is too complex to methodically model, or systematic, where a clear correlation exists between a process parameter and the resulting

physical device variation [72]. Often process variation is also classified as intradie, being between

two devices within a die, interdie, two separate dies in a wafer, or wafer-to-wafer.

Device Geometry refers to the shape of the devices created through lithography. Specifically, we are interested in the length, width, and oxide thickness of the transistor and the shape of the interconnect wire. Given that photolithography’s primary goal is to define geometries on the wafer, it should come as no surprise that almost every step has the potential to introduce variation into the shape of the device.

In order to produce sub-wavelength features, the lithographic mask has to be carefully designed to account for the many interactions of light that will occur during image transfer on to the pho- toresist. Despite the advanced resolution enhancement techniques employed, diffraction patterns from adjacent lines will change the line width of the feature being printed. These proximity effects are most evident at the lower layers where smaller features are more common. Also metal wires

tend to exhibit line end shortening and corner rounding as a result of the light interactions [48].

A major source of variation in both wires and transistors is known as Line Edge Roughness (LER) and Line Width Roughness (LWR). LER manifest as jagged edges in geometries on the wafer and LWR is the resulting variation in width due to LER. The main sources of LER are light interactions, etching, and defocus, where the mask image is not sharply defined on the surface of the resist. Defocus, in turn, has several causes, these include mask misalignment and tilt, change in the refractive index of the reduction lenses due to heat from the energy source, and variations in the resist thickness leading from variations on the wafer surface induced by chemical-mechanical polishing. As identified by the ITRS, while circuits continue to scale, “LER of photoresist has

substantially sustained the same absolute value”, on the order of 5nm [76], “and therefore has

attained an even larger percentage of [the random variation]”[2].

In addition to its LER contributions, defocus has a systematic effect on line width that corre- lates with the density of the design, where dense features have increased line width, and decreased

line widths correlate with isolated features [98]. This effect can be reduced by adding features

to the lithographic mask in order to maintain relatively constant density, however, these features may cause undesired light interactions, further contributing to the overall geometric variation.

Finally, chemical-mechanical polishing directly affects the shape of the interconnect since every wire layer gets polished before processing for the next layer can begin. This polishing introduces a systematic variation in the layer thickness that is, in part, dependent on the density of the

patterns being polished [43].

Gate Oxide Thickness defines the thickness of the oxide separating the transistor’s channel from the gate. The gate oxide is created through an iteration of the manufacturing processes and therefore, is subject to variation induced by the process. To maintain good control, the gate oxide thickness has kept up with transistor scaling. However, as the ITRS notes, a “particu- larly challenging issue is the control of the thickness, including its variability, of these ultra-thin

MOSFETs” [2]. As such, a thickness variation of one or two atomic layers, now accounts for

a significant variation percent. At these dimensions, gate tunneling becomes a significant issue,

therefore, to alleviate this problem, newer technology nodes have moved to using high-κdielectrics.

The high-κdielectrics allow for thicker oxides, while providing an Equivalent Oxide Thickness of

approximately 1 nm or about 5 atomic layers [49, 67], maintaining the control provided by thin

SiO2dielectrics. However, this technology comes with its own variation challenges since its poly-

crystalline structure is prone to inhomogeneities, that directly affect the electrical properties of

the device [20, 15].

Random Dopant Fluctuations represent the uncertainty of charge concentration and loca- tion within the transistor’s doped regions. The process of ion implantation followed by thermal

annealing is inherently nondeterministic and can be modeled by a Poisson distribution [67], lead-

ing to the random nature of this variation source. Moreover, as device size scales down, the law of large numbers no longer applies, and therefore, the magnitude of this random variation increases [45]

Figure 2.3: σVth as a function of technology nodes, based on predictive technology models. Con- sidering the individual effects of random dopant fluctuations (RDF), line edge roughness (LER)

and oxide thickness (OTF) from [99]