Method Goal and General Steps

The main characteristics to be covered by a virtual architecture to bring the mentioned flexibility, reliability and scalability are listed below:

40 2.4 Virtual Architectures for Partial RunTime Reconfigurable Systems. Design Method

1. Core Relocation. Relocation is very important because it leads to memory savings and simplifies the SW control system. Relocation permits to keep a unique image of the hard core and allocate it at runtime at the proper position in the virtual architecture. Otherwise, as much images of the hard core as possible slot positions have to be kept in memory.

2. The possibility of loading hard cores of any size in the system that also brings flexibility.

3. The architecture has to permit the exploitation of as much FPGA specific resources as possible (high use of the on-chip resources).

4. The internal communication has to permit the system to be scalable.

5. To permits non intrusive partial runtime reconfiguration. This means that the on-chip communication infrastructure has to be kept active during reconfiguration.

This is not a trivial task because usually the communication infrastructure is spread across the chip.

The design steps proposed in this subsection along with the guidelines presented in the next subsection, more specific to Xilinx FPGAs, aim to lead to the design of reconfigurable systems VAs that have the characteristics previously listed. A general view of the method design steps can be found in Figure 2.11 and its description is included next:

1. Reconfiguration grain and requirements definition

2. FPGA logic distribution analysis

3. Resource division into fixed and reconfigurable areas

4. Slots model and distribution selection

5. Internal communication definition (model and resources)

Figure 2.11: Virtual architectures for partial runtime reconfigurable systems - design method general steps.

1. The first step is to defined the requirements to be covered by the reconfigurable system. Regarding VAs, it is important to define the type and the granularity of the reconfiguration or reconfigurations that will be supported. For systems with

2.4 Virtual Architectures for Partial RunTime Reconfigurable Systems. Design Method 41

fine grain, Intra-Module, reconfiguration (some LUTs, single BRAMs and/or some FFs) there is no need of defining a special architecture. The restrictions required to successfully perform a partial reconfiguration, to know the position of the logic to be modified, can be setup during hard core design. This type of reconfiguration will be called hard core adaptation or small bit manipulation (the Xilinx term). On the other hand, VAs are needed for medium and/or coarse grain reconfigurations of Intra-Module or Inter-Module type.

2. Once a partially reconfigurable FPGA that covers the defined area requirements and reconfiguration method(s) has been selected, the FPGA logic distribution has to be analyzed. The aim at this point is to identify the specific elements distribution homogeneity. Specific elements could be: embedded memories, DSP blocks, multipliers, configuration ports, clock controller, ADCs, etc.

3. The next step is to define the FPGA internal resource division into fixed and reconfigurable area. The main goal in this step is to select such distribution that the resulting reconfigurable area is as homogeneous as possible. All elements that have a non regular distribution should be assigned to the fixed FPGA area (like the ICAP port in Xilinx FPGAs). For instance, if the IOBs distribution across the die is regular, then IOBs can be assigned to the reconfigurable area. In the opposite case, they have to be part of the fixed area and to be accessed using macro structures.

4. Once the fixed/reconfigurable area resource division has been defined, the next step is to divide the reconfigurable area into homogeneous reconfigurable modules, called slots that allocate hard cores. Each slot has to guarantee hard cores access to the maximum amount of FPGA specific resources, as well as to the on-chip communication infrastructure. If it is foreseen that all hard cores in the final application require access to the same FPGA embedded resources, like multipliers, then this resource, if it is possible and homogeneity is preserved, will be considered as part of each slot. As it can be noticed from the state of the art, the reconfigurable area can be divided into slots following two models: one dimensional (1D) and two dimensional (2D).

5. The last step, but maybe the most important, is to define the internal communication of the reconfigurable system. The selection of the communication scheme depends on the required system flexibility and scalability. For simple systems, where there is no need of hard core relocation and the amount of slots is kept low (one or two), simple direct connections are the best options (like in the Xilinx approach). On the other hand for robust and flexible systems, bus (like the H ¨ubner et al. approach) and NoC type internal communication schemes are more suitable. Anyhow, independently from the communication scheme, if flexibility and reliability are targeted, the underlying physical implementation layer has to be prepared for that. The communication structure has to be localized in an FPGA area that is reserved for the internal communication. This permits to keep it active during reconfiguration, even when relocation is being performed.

Also, the occupied area has to be kept as low as possible and access to the communication infrastructure has to be guaranteed for all possible slot positions.

Another, important, aspect of the physical implementation is to carefully select the communication interconnection building elements and the amount of these

42 2.4 Virtual Architectures for Partial RunTime Reconfigurable Systems. Design Method

elements to be used, because this will define the interconnection delay, the data transfer rates and the required area. This selection depends on the target FPGA family and will be discussed with an example in the next subsection.